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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti,phy-j721e-wiz.yaml61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
90 const: 0
113 "^pll[0|1]-refclk$":
126 const: 0
157 const: 0
166 "^serdes@[0-9a-f]+$":
210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
214 ranges = <0x5000000 0x500000
[all...]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dhisi504-nand.txt31 reg = <0x4020000 0x10000>, <0x5000000 0x1000>;
32 interrupts = <0 379 4>;
40 partition@0 {
42 reg = <0x00000000 0x00400000>;
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,k3-m4f-rproc.yaml92 reg = <0x00 0x9cb00000 0x00 0x100000>;
98 reg = <0x00 0x9cc00000 0x00 0xe00000>;
107 mailbox0_cluster0: mailbox-0 {
113 reg = <0x00 0x5000000 0x00 0x30000>,
114 <0x00 0x5040000 0x00 0x10000>;
123 ti,sci-proc-ids = <0x18 0xff>;
/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep93xx-edb9302.dts17 memory@0 {
20 reg = <0x0000000 0x800000>,
21 <0x1000000 0x800000>,
22 <0x4000000 0x800000>,
23 <0x5000000 0x800000>;
34 led-0 {
36 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
56 reg = <0x60000000 0x1000000>;
66 gpio-ranges = <&syscon 0 153 1>,
77 gpio-ranges = <&syscon 0 143 1>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dgpu.txt54 reg = <0xfdb00000 0x10000>;
67 iommus = <&gpu_iommu 0>;
74 reg = <0xfdd00000 0x2000>,
75 <0xfec00000 0x180000>;
87 gpu_sram: gpu-sram@0 {
88 reg = <0x0 0x100000>;
89 ranges = <0 0 0xfec00000 0x100000>;
103 reg = <0x5000000 0x40000>, <0x509e000 0x10>;
115 iommus = <&adreno_smmu 0>;
H A Dgpu.yaml32 - pattern: '^qcom,adreno-[0-9a-f]{8}$'
38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$'
44 - pattern: '^amd,imageon-200\.[0-1]$'
149 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$'
225 pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
252 reg = <0xfdb00000 0x10000>;
266 iommus = <&gpu_iommu 0>;
273 reg = <0xfdd00000 0x2000>,
274 <0xfec00000 0x180000>;
283 ranges = <0 0xfec00000 0x100000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8916-gplus-fl8005a.dts36 ocv-capacity-table-0 =
46 <3310000 1>, <3000000 0>;
55 pinctrl-0 = <&camera_flash_default>;
68 pinctrl-0 = <&gpio_keys_default>;
81 pinctrl-0 = <&gpio_leds_default>;
102 pinctrl-0 = <&usb_id_default>;
113 reg = <0x38>;
128 pinctrl-0 = <&touchscreen_default>;
138 reg = <0x0 0x86800000 0x0 0x5000000>;
174 pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
H A Dmsm8916-longcheer-l8910.dts34 pinctrl-0 = <&spk_ext_pa_default>;
43 pinctrl-0 = <&camera_front_flash_default>;
57 pinctrl-0 = <&gpio_keys_default>;
71 led-0 {
78 pinctrl-0 = <&button_backlight_default>;
86 pinctrl-0 = <&usb_id_default>;
95 reg = <0x30>;
97 #size-cells = <0>;
102 pinctrl-0 = <&status_led_default>;
110 #size-cells = <0>;
[all …]
H A Dmsm8916-longcheer-l8150.dts30 * It must be loaded at 0x8b600000. Unfortunately, this also means that
31 * mpss_mem does not fit when loaded to the typical address at 0x86800000.
35 * boot when placed at 0x8a800000 to 0x8e800000.
42 reg = <0x0 0x8b600000 0x0 0x600000>;
47 reg = <0x0 0x8e800000 0x0 0x5000000>;
60 ocv-capacity-table-0 = <4330000 100>, <4265000 95>,
68 <3000000 0>;
75 pinctrl-0 = <&gpio_keys_default>;
97 pinctrl-0 = <&ctp_pwr_en_default>;
106 pinctrl-0 = <&camera_flash_default>;
[all …]
H A Dmsm8916-samsung-fortuna-common.dtsi25 reg = <0x0 0x85a00000 0x0 0x600000>;
38 pwms = <&clk_pwm 0 100000>;
42 brightness-levels = <0 255>;
46 pinctrl-0 = <&backlight_en_default>;
56 pinctrl-0 = <&backlight_pwm_default>;
63 pinctrl-0 = <&gpio_keys_default>;
90 sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
93 pinctrl-0 = <&nfc_i2c_default>;
97 #size-cells = <0>;
101 reg = <0x27>;
[all …]
H A Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsunxi-d1s-t113.dtsi21 #clock-cells = <0>;
39 reg = <0x2000000 0x800>;
150 reg = <0x2001000 0x1000>;
161 reg = <0x2009000 0x400>;
172 reg = <0x2031000 0x400>;
181 #sound-dai-cells = <0>;
187 reg = <0x2033000 0x1000>;
196 #sound-dai-cells = <0>;
202 reg = <0x2034000 0x1000>;
211 #sound-dai-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
67 reg = <0x0 0x6020000 0 0x20000>;
73 reg = <0x0 0x1e60000 0x0 0x4>;
[all …]
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
H A Dfsl-lx2160a.dtsi12 /memreserve/ 0x80000000 0x00010000;
26 #size-cells = <0>;
29 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
38 i-cache-size = <0xC000>;
50 reg = <0x1>;
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
[all …]
/freebsd/contrib/sqlite3/
H A Dsqlite3.c130 #define HAVE_LOG2 0
163 #define SQLITE_OS_OTHER 0
166 #define SQLITE_ENABLE_LOCKING_STYLE 0
170 #define OS_VXWORKS 0
213 ** value of 0 means that compiler is not being used. The
215 ** optimizations, and hence set all compiler macros to 0
227 # define GCC_VERSION 0
232 # define MSVC_VERSION 0
240 # if MSVC_VERSION==0 || MSVC_VERSION>=1800
243 # define SQLITE_HAVE_C99_MATH_FUNCS (0)
[all …]