| /linux/arch/alpha/kernel/ |
| H A D | sys_takara.c | 41 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in takara_update_irq_hw()
42 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in takara_update_irq_hw()
43 outl(mask & 0xffff0000UL, regaddr); in takara_update_irq_hw()
77 * The PALcode will have passed us vectors 0x800 or 0x810, in takara_device_interrupt()
92 intstatus = inw(0x500) & 15; in takara_device_interrupt()
102 if (intstatus & 1) handle_irq(16+0); in takara_device_interrupt()
111 int irq = (vector - 0x800) >> 4; in takara_srm_device_interrupt()
125 unsigned int ctlreg = inl(0x500); in takara_init_irq()
128 ctlreg &= ~0x8000; in takara_init_irq()
129 outl(ctlreg, 0x500); in takara_init_irq()
[all …]
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| /linux/include/dt-bindings/clock/ |
| H A D | lpc18xx-ccu.h | 13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
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| /linux/arch/powerpc/platforms/52xx/ |
| H A D | mpc52xx_pm.c | 35 return 0; in mpc52xx_pm_valid()
51 tmp &= ~(0x3 << (pin * 2)); in mpc52xx_set_wakeup_gpio()
57 return 0; in mpc52xx_set_wakeup_gpio()
75 if (of_address_to_resource(np, 0, &res)) { in mpc52xx_pm_prepare()
81 mbar = ioremap(res.start, 0xc000); /* we should map whole region including SRAM */ in mpc52xx_pm_prepare()
89 sdram = mbar + 0x100; in mpc52xx_pm_prepare()
90 cdm = mbar + 0x200; in mpc52xx_pm_prepare()
91 intr = mbar + 0x500; in mpc52xx_pm_prepare()
92 gpiow = mbar + 0xc00; in mpc52xx_pm_prepare()
93 sram = mbar + 0x8000; /* Those will be handled by the */ in mpc52xx_pm_prepare()
[all …]
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| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | pq3-rmu-0.dtsi | 2 * PQ3 RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
42 message-unit@0 {
44 reg = <0x0 0x100>;
46 53 2 0 0 /* msg1_tx_irq */
47 54 2 0 0>;/* msg1_rx_irq */
51 reg = <0x100 0x100>;
53 55 2 0 0 /* msg2_tx_irq */
54 56 2 0 0>;/* msg2_rx_irq */
[all …]
|
| H A D | qoriq-rmu-0.dtsi | 2 * QorIQ RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
42 message-unit@0 {
44 reg = <0x0 0x100>;
46 60 2 0 0 /* msg1_tx_irq */
47 61 2 0 0>;/* msg1_rx_irq */
51 reg = <0x100 0x100>;
53 62 2 0 0 /* msg2_tx_irq */
54 63 2 0 0>;/* msg2_rx_irq */
[all …]
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| /linux/arch/s390/include/asm/ |
| H A D | kvm_para.h | 16 * use 0x500 as KVM hypercall
28 #define HYPERCALL_FMT_1 , "0" (r2)
79 " diag 2,4,0x500" \
93 GENERATE_KVM_HYPERCALL_FUNC(0)
110 return 0; in kvm_arch_para_features()
115 return 0; in kvm_arch_para_hints()
|
| /linux/drivers/media/usb/stk1160/ |
| H A D | stk1160-reg.h | 14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
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| /linux/drivers/bus/ |
| H A D | omap_l3_noc.h | 16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp.dtsi | 35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
41 reg = <0x1400 0x500>;
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
55 pinctrl-0 = <&uart2_pins>;
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
67 pinctrl-0 = <&uart3_pins>;
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
[all …]
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | toshiba,tc358775.yaml | 30 description: i2c address of the bridge, 0x0f
50 port@0:
83 - port@0
115 reg = <0x078b8000 0x500>;
118 #size-cells = <0>;
122 reg = <0x0f>;
132 #size-cells = <0>;
134 port@0 {
135 reg = <0>;
153 reg = <0x1a98000 0x25c>;
[all …]
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | microchip,csi2dc.yaml | 76 port@0:
129 - port@0
147 reg = <0xe1404000 0x500>;
153 #size-cells = <0>;
154 port@0 {
155 reg = <0>; /* must be 0, first child port */
177 reg = <0xe1404000 0x500>;
185 #size-cells = <0>;
186 port@0 {
187 reg = <0>; /* must be 0, first child port */
|
| /linux/drivers/net/ethernet/ibm/ehea/ |
| H A D | ehea_hw.h | 37 u64 qpx_reserved1[(0x098 - 0x058) / 8];
39 u64 qpx_reserved2[(0x100 - 0x0A0) / 8];
43 u64 qpx_reserved3[(0x140 - 0x118) / 8];
45 u64 qpx_reserved4[(0x170 - 0x148) / 8];
47 u64 qpx_reserved5[(0x1B0 - 0x178) / 8];
53 u64 qpx_reserved6[(0x220 - 0x1D8) / 8];
55 u64 qpx_reserved7[(0x240 - 0x228) / 8];
62 u64 qpx_reserved8[(0x300 - 0x270) / 8];
78 u64 qpx_reserved9[(0x400 - 0x378) / 8];
79 u64 reserved_ext[(0x500 - 0x400) / 8];
[all …]
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| /linux/include/soc/imx/ |
| H A D | cpu.h | 15 #define MXC_CPU_IMX6SL 0x60
16 #define MXC_CPU_IMX6DL 0x61
17 #define MXC_CPU_IMX6SX 0x62
18 #define MXC_CPU_IMX6Q 0x63
19 #define MXC_CPU_IMX6UL 0x64
20 #define MXC_CPU_IMX6ULL 0x65
22 #define MXC_CPU_IMX6ULZ 0x6b
23 #define MXC_CPU_IMX6SLL 0x67
24 #define MXC_CPU_IMX7D 0x72
25 #define MXC_CPU_IMX7ULP 0xff
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/marvell/ |
| H A D | mvebu-system-controller.txt | 17 reg = <0xd0018200 0x500>;
|
| /linux/tools/perf/arch/powerpc/util/ |
| H A D | book3s_hv_exits.h | 10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | marvell,mvebu-sdram-controller.yaml | 30 reg = <0x1400 0x500>;
|
| /linux/arch/powerpc/kvm/ |
| H A D | trace_book3s.h | 10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | jcore,aic.yaml | 40 reg = <0x200 0x30>, <0x500 0x30>;
|
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | jcore,pit.yaml | 41 reg = <0x200 0x30 0x500 0x30>;
42 interrupts = <0x48>;
|
| /linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | apple,efuses.yaml | 42 reg = <0x3d2bc000 0x1000>;
47 reg = <0x500 0x8>;
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dm816x-clocks.dtsi | 7 reg = <0x400 0x40>;
23 reg = <0x440 0x30>;
35 reg = <0x470 0x30>;
46 reg = <0x4a0 0x30>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
83 /* 0x48180000 */
86 #clock-cells = <0>;
[all …]
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| /linux/include/dt-bindings/reset/ |
| H A D | hisi,hi6220-resets.h | 9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
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| /linux/arch/powerpc/platforms/83xx/ |
| H A D | mpc83xx.h | 8 #define MPC83XX_SCCR_OFFS 0xA08
9 #define MPC83XX_SCCR_USB_MASK 0x00f00000
10 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
11 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
12 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
13 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
14 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
15 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
16 #define MPC8315_SCCR_USB_MASK 0x00c00000
17 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
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| /linux/arch/arm/mach-omap2/ |
| H A D | omap4-sar-layout.h | 14 #define SAR_BANK1_OFFSET 0x0000
15 #define SAR_BANK2_OFFSET 0x1000
16 #define SAR_BANK3_OFFSET 0x2000
17 #define SAR_BANK4_OFFSET 0x3000
20 #define SCU_OFFSET0 0xfe4
21 #define SCU_OFFSET1 0xfe8
22 #define OMAP_TYPE_OFFSET 0xfec
23 #define L2X0_SAVE_OFFSET0 0xff0
24 #define L2X0_SAVE_OFFSET1 0xff4
25 #define L2X0_AUXCTRL_OFFSET 0xff8
[all …]
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| /linux/Documentation/devicetree/bindings/thermal/ |
| H A D | nvidia,tegra30-tsensor.yaml | 64 reg = <0x70014000 0x500>;
65 interrupts = <0 102 4>;
|