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/linux/drivers/net/wireless/ath/ath9k/
H A Dreg_aic.h20 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
21 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
22 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
23 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
24 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
26 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
27 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
28 #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
30 #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
31 #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-7040.dtsi14 <0x0 &smmu 0x480 0x20>,
15 <0x100 &smmu 0x4a0 0x20>,
16 <0x200 &smmu 0x4c0 0x20>;
17 iommu-map-mask = <0x031f>;
21 iommus = <&smmu 0x444>;
25 iommus = <&smmu 0x445>;
29 iommus = <&smmu 0x440>;
33 iommus = <&smmu 0x441>;
H A Dcn9130-crb-A.dts17 phys = <&cp0_comphy0 0
18 &cp0_comphy1 0
19 &cp0_comphy2 0
20 &cp0_comphy3 0>;
22 <0x0 &smmu 0x480 0x20>,
23 <0x100 &smmu 0x4a0 0x20>,
24 <0x200 &smmu 0x4c0 0x20>;
25 iommu-map-mask = <0x031f>;
H A Darmada-8040.dtsi14 <0x0 &smmu 0x480 0x20>,
15 <0x100 &smmu 0x4a0 0x20>,
16 <0x200 &smmu 0x4c0 0x20>;
17 iommu-map-mask = <0x031f>;
30 iommus = <&smmu 0x444>;
34 iommus = <&smmu 0x445>;
38 iommus = <&smmu 0x440>;
42 iommus = <&smmu 0x441>;
46 iommus = <&smmu 0x454>;
50 iommus = <&smmu 0x450>;
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A Domap_dmm_priv.h11 #define DMM_REVISION 0x000
12 #define DMM_HWINFO 0x004
13 #define DMM_LISA_HWINFO 0x008
14 #define DMM_DMM_SYSCONFIG 0x010
15 #define DMM_LISA_LOCK 0x01C
16 #define DMM_LISA_MAP__0 0x040
17 #define DMM_LISA_MAP__1 0x044
18 #define DMM_TILER_HWINFO 0x208
19 #define DMM_TILER_OR__0 0x220
20 #define DMM_TILER_OR__1 0x224
[all …]
/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux/drivers/soc/imx/
H A Dsoc-imx.c16 #define IIM_UID 0x820
18 #define OCOTP_UID_H 0x420
19 #define OCOTP_UID_L 0x410
21 #define OCOTP_ULP_UID_1 0x4b0
22 #define OCOTP_ULP_UID_2 0x4c0
23 #define OCOTP_ULP_UID_3 0x4d0
24 #define OCOTP_ULP_UID_4 0x4e0
34 u64 soc_uid = 0; in imx_soc_device_init()
41 return 0; in imx_soc_device_init()
155 soc_uid = val & 0xffff; in imx_soc_device_init()
[all …]
/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7710.c19 UNUSED = 0,
33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
41 INTC_VECT(IPSEC, 0xbe0),
43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
[all …]
H A Dsetup-sh7705.c20 UNUSED = 0,
36 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
39 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
40 INTC_VECT(SCIF0, 0x8e0),
41 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
42 INTC_VECT(SCIF2, 0x960),
43 INTC_VECT(ADC_ADI, 0x980),
44 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
[all …]
H A Dsetup-sh770x.c24 UNUSED = 0,
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
[all …]
H A Dsetup-sh7720.c26 [0] = {
27 .start = 0xa413fec0,
28 .end = 0xa413fec0 + 0x28 - 1,
33 .start = evt2irq(0x480),
59 DEFINE_RES_MEM(0xa4430000, 0x100),
60 DEFINE_RES_IRQ(evt2irq(0xc00)),
65 .id = 0,
80 DEFINE_RES_MEM(0xa4438000, 0x100),
81 DEFINE_RES_IRQ(evt2irq(0xc20)),
95 [0] = {
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7770.c22 DEFINE_RES_MEM(0xff923000, 0x100),
23 DEFINE_RES_IRQ(evt2irq(0x9a0)),
28 .id = 0,
42 DEFINE_RES_MEM(0xff924000, 0x100),
43 DEFINE_RES_IRQ(evt2irq(0x9c0)),
62 DEFINE_RES_MEM(0xff925000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x9e0)),
82 DEFINE_RES_MEM(0xff926000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0xa00)),
102 DEFINE_RES_MEM(0xff927000, 0x100),
[all …]
H A Dsetup-sh7734.c32 DEFINE_RES_MEM(0xffe40000, 0x100),
33 DEFINE_RES_IRQ(evt2irq(0x8c0)),
38 .id = 0,
53 DEFINE_RES_MEM(0xffe41000, 0x100),
54 DEFINE_RES_IRQ(evt2irq(0x8e0)),
74 DEFINE_RES_MEM(0xffe42000, 0x100),
75 DEFINE_RES_IRQ(evt2irq(0x900)),
95 DEFINE_RES_MEM(0xffe43000, 0x100),
96 DEFINE_RES_IRQ(evt2irq(0x920)),
116 DEFINE_RES_MEM(0xffe44000, 0x100),
[all …]
/linux/arch/powerpc/platforms/83xx/
H A Dmpc832x_rdb.c48 unsigned int i = 0; in of_fsl_spi_probe()
60 memset(res, 0, sizeof(res)); in of_fsl_spi_probe()
77 for (j = 0; j < num_board_infos; j++) { in of_fsl_spi_probe()
85 ret = of_address_to_resource(np, 0, &res[0]); in of_fsl_spi_probe()
89 ret = of_irq_to_resource(np, 0, &res[1]); in of_fsl_spi_probe()
90 if (ret <= 0) in of_fsl_spi_probe()
149 pr_debug("%s %d %d\n", __func__, spi_get_chipselect(spi, 0), on); in mpc83xx_spi_cs_control()
158 .bus_num = 0x4c0,
159 .chip_select = 0,
169 par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */ in mpc832x_spi_init()
[all …]
/linux/arch/arm/mach-orion5x/
H A Dorion5x.h36 #define ORION5X_REGS_PHYS_BASE 0xf1000000
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm6856.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0x0 0x0 0x81000000 0x8000>;
87 reg = <0x1000 0x1000>, /* GICD */
88 <0x2000 0x2000>, /* GICC */
89 <0x4000 0x2000>, /* GICH */
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6878.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
[all …]
H A Dbcm6855.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0 0x81000000 0x8000>;
106 reg = <0x1000 0x1000>,
[all …]
/linux/drivers/net/ethernet/apple/
H A Dbmac.h17 #define XIFC 0x000 /* low-level interface control */
18 # define TxOutputEnable 0x0001 /* output driver enable */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
21 # define MIILoopbackBits 0x0006
22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
23 # define SQETestEnable 0x0010 /* SQE test enable */
24 # define SQETimeWindow 0x03e0 /* SQE time window */
25 # define XIFLanceMode 0x0010 /* Lance mode enable */
26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8568si-post.dtsi39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
43 /* controller at 0x8000 */
47 interrupts = <24 0x2 0 0>;
48 bus-range = <0 0xff>;
52 sleep = <&pmc 0x80000000>;
55 /* controller at 0xa000 */
61 bus-range = <0 255>;
63 interrupts = <26 2 0 0>;
64 sleep = <&pmc 0x20000000>;
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0>;
49 reg = <0xe0028000 0x1000>,
50 <0xe0020000 0x0100>;
62 reg = <0xe0110000 0x10000>;
64 #size-cells = <0>;
69 #clock-cells = <0>;
71 iic0_sclkdiv: iic0_sclkdiv@624,0 {
73 reg = <0x624 0>;
[all …]

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