/linux/drivers/net/ethernet/intel/ice/ |
H A D | ice_ptp_consts.h | 17 0x092000, 18 0x126000, 19 0x1BA000, 20 0x24E000, 21 0x2E2000, 24 0x98, 30 0x093000, 31 0x127000, 32 0x1BB000, 33 0x24F000, [all …]
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H A D | ice_ptp_hw.h | 131 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0) 222 ICE_RCLKA_PIN = 0, /* SCL pin */ 232 ZL_REF0P = 0, 246 ZL_OUT0 = 0, 257 SI_REF0P = 0, 269 SI_OUT0 = 0, 326 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL 420 #define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL 421 #define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL 422 #define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL [all …]
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/linux/drivers/net/wireless/broadcom/b43/ |
H A D | phy_lcn.c | 66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup() 67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup() 70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup() 71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup() 72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup() 73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup() 74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup() 75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup() 76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup() 77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup() [all …]
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/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | fsl,imx8m-pinctrl.yaml | 81 reg = <0x30330000 0x10000>; 85 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, 86 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | pci_nrtr_regs.h | 22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100 24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120 26 #define mmPCI_NRTR_DBG_E_ARB 0x300 28 #define mmPCI_NRTR_DBG_W_ARB 0x304 30 #define mmPCI_NRTR_DBG_N_ARB 0x308 32 #define mmPCI_NRTR_DBG_S_ARB 0x30C 34 #define mmPCI_NRTR_DBG_L_ARB 0x310 36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320 38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324 40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328 [all …]
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
H A D | phy_lcn.c | 40 #define NOISE_IF_OFF 0 45 #define PAPD2LUT 0 46 #define PAPD_CORR_NORM 0 47 #define PAPD_BLANKING_THRESHOLD 0 48 #define PAPD_STOP_AFTER_LAST_UPDATE 0 70 (0 + 8) 72 (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT) 75 (0 + 8) 77 (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT) 85 (read_phy_reg((pi), 0x451) & \ [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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/linux/drivers/ntb/hw/amd/ |
H A D | ntb_hw_amd.h | 56 #define NTB_LNK_STA_SPEED_MASK 0x000F0000 57 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000 97 AMD_CNTL_OFFSET = 0x200, 106 AMD_STA_OFFSET = 0x204, 107 AMD_PGSLV_OFFSET = 0x208, 108 AMD_SPAD_MUX_OFFSET = 0x20C, 109 AMD_SPAD_OFFSET = 0x210, 110 AMD_RSMU_HCID = 0x250, 111 AMD_RSMU_SIID = 0x254, 112 AMD_PSION_OFFSET = 0x300, [all …]
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/linux/drivers/clk/tegra/ |
H A D | clk-tegra-audio.c | 17 #define AUDIO_SYNC_CLK_I2S0 0x4a0 18 #define AUDIO_SYNC_CLK_I2S1 0x4a4 19 #define AUDIO_SYNC_CLK_I2S2 0x4a8 20 #define AUDIO_SYNC_CLK_I2S3 0x4ac 21 #define AUDIO_SYNC_CLK_I2S4 0x4b0 22 #define AUDIO_SYNC_CLK_SPDIF 0x4b4 23 #define AUDIO_SYNC_CLK_DMIC1 0x560 24 #define AUDIO_SYNC_CLK_DMIC2 0x564 25 #define AUDIO_SYNC_CLK_DMIC3 0x6b8 27 #define AUDIO_SYNC_DOUBLER 0x49c [all …]
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/linux/drivers/net/ethernet/broadcom/asp2/ |
H A D | bcmasp_intf_defs.h | 6 ((((intf)->port) * 0x800) + 0xc000) 7 #define UMC_CMD 0x008 8 #define UMC_CMD_TX_EN BIT(0) 10 #define UMC_CMD_SPEED_SHIFT 0x2 11 #define UMC_CMD_SPEED_MASK 0x3 12 #define UMC_CMD_SPEED_10 0x0 13 #define UMC_CMD_SPEED_100 0x1 14 #define UMC_CMD_SPEED_1000 0x2 15 #define UMC_CMD_SPEED_2500 0x3 33 #define UMC_MAC0 0x0c [all …]
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/linux/drivers/phy/ralink/ |
H A D | phy-mt7621-pci.c | 18 #define RG_PE1_PIPE_REG 0x02c 22 #define RG_P0_TO_P1_WIDTH 0x100 23 #define RG_PE1_H_LCDDS_REG 0x49c 24 #define RG_PE1_H_LCDDS_PCW GENMASK(30, 0) 26 #define RG_PE1_FRC_H_XTAL_REG 0x400 30 #define RG_PE1_FRC_PHY_REG 0x000 34 #define RG_PE1_H_PLL_REG 0x490 42 #define RG_PE1_H_PLL_FBKSEL_REG 0x4bc 45 #define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4 46 #define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0) [all …]
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/linux/drivers/media/pci/cx18/ |
H A D | cx18-av-core.h | 32 CX18_AV_SVIDEO_LUMA1 = 0x10, 33 CX18_AV_SVIDEO_LUMA2 = 0x20, 34 CX18_AV_SVIDEO_LUMA3 = 0x30, 35 CX18_AV_SVIDEO_LUMA4 = 0x40, 36 CX18_AV_SVIDEO_LUMA5 = 0x50, 37 CX18_AV_SVIDEO_LUMA6 = 0x60, 38 CX18_AV_SVIDEO_LUMA7 = 0x70, 39 CX18_AV_SVIDEO_LUMA8 = 0x80, 40 CX18_AV_SVIDEO_CHROMA4 = 0x400, 41 CX18_AV_SVIDEO_CHROMA5 = 0x500, [all …]
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/linux/drivers/gpu/drm/radeon/ |
H A D | sumod.h | 30 #define RCU_FW_VERSION 0x30c 32 #define RCU_PWR_GATING_SEQ0 0x408 33 #define RCU_PWR_GATING_SEQ1 0x40c 34 #define RCU_PWR_GATING_CNTL 0x410 35 # define PWR_GATING_EN (1 << 0) 36 # define RSVD_MASK (0x3 << 1) 38 # define PCV_MASK (0x1f << 3) 41 # define PCP_MASK (0xf << 8) 44 # define RPW_MASK (0xf << 16) 47 # define ID_MASK (0xf << 24) [all …]
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/linux/drivers/clk/stm32/ |
H A D | stm32mp25_rcc.h | 10 #define RCC_SECCFGR0 0x0 11 #define RCC_SECCFGR1 0x4 12 #define RCC_SECCFGR2 0x8 13 #define RCC_SECCFGR3 0xC 14 #define RCC_PRIVCFGR0 0x10 15 #define RCC_PRIVCFGR1 0x14 16 #define RCC_PRIVCFGR2 0x18 17 #define RCC_PRIVCFGR3 0x1C 18 #define RCC_RCFGLOCKR0 0x20 19 #define RCC_RCFGLOCKR1 0x24 [all …]
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/linux/drivers/clk/hisilicon/ |
H A D | clk-hi6220.c | 23 { HI6220_REF32K, "ref32k", NULL, 0, 32764, }, 24 { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, }, 25 { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, }, 26 { HI6220_MMC2_PAD, "mmc2_pad", NULL, 0, 100000000, }, 27 { HI6220_MMC0_PAD, "mmc0_pad", NULL, 0, 200000000, }, 28 { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, }, 29 { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,}, 30 { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,}, 31 { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,}, 32 { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,}, [all …]
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/linux/drivers/usb/typec/mux/ |
H A D | wcd939x-usbss.c | 18 #define WCD_USBSS_PMP_OUT1 0x2 20 #define WCD_USBSS_DP_DN_MISC1 0x20 23 #define WCD_USBSS_DP_DN_MISC1_DN_PCOMP_2X_DYN_BST_ON_EN BIT(0) 25 #define WCD_USBSS_MG1_EN 0x24 29 #define WCD_USBSS_MG1_BIAS 0x25 33 #define WCD_USBSS_MG1_MISC 0x27 37 #define WCD_USBSS_MG2_EN 0x28 41 #define WCD_USBSS_MG2_BIAS 0x29 45 #define WCD_USBSS_MG2_MISC 0x30 49 #define WCD_USBSS_DISP_AUXP_THRESH 0x80 [all …]
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/linux/drivers/memory/tegra/ |
H A D | tegra210-emc.h | 21 #define EMC_INTSTATUS 0x0 23 #define EMC_DBG 0x8 26 #define EMC_CFG 0xc 31 #define EMC_PIN 0x24 32 #define EMC_PIN_PIN_CKE BIT(0) 35 #define EMC_TIMING_CONTROL 0x28 36 #define EMC_RC 0x2c 37 #define EMC_RFC 0x30 38 #define EMC_RAS 0x34 39 #define EMC_RP 0x38 [all …]
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H A D | tegra186.c | 22 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) 50 for (i = 0; i < mc->soc->num_channels; i++) { in tegra186_mc_probe() 60 if (err < 0) in tegra186_mc_probe() 63 return 0; in tegra186_mc_probe() 78 if (client->regs.sid.security == 0 && client->regs.sid.override == 0) in tegra186_mc_client_sid_override() 82 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { in tegra186_mc_client_sid_override() 97 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0); in tegra186_mc_client_sid_override() 118 unsigned int i, index = 0; in tegra186_mc_probe_device() 122 return 0; in tegra186_mc_probe_device() 126 if (args.np == mc->dev->of_node && args.args_count != 0) { in tegra186_mc_probe_device() [all …]
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