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/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dqt202x_phy.c28 #define MDIO_QUAKE_LED0_REG (0xD006)
31 #define PCS_FW_HEARTBEAT_REG 0xd7ee
32 #define PCS_FW_HEARTB_LBN 0
34 #define PCS_FW_PRODUCT_CODE_1 0xd7f0
35 #define PCS_FW_VERSION_1 0xd7f3
36 #define PCS_FW_BUILD_1 0xd7f6
37 #define PCS_UC8051_STATUS_REG 0xd7fd
38 #define PCS_UC_STATUS_LBN 0
40 #define PCS_UC_STATUS_FW_SAVE 0x20
41 #define PMA_PMD_MODE_REG 0xc301
[all …]
/linux/drivers/media/usb/hdpvr/
H A Dhdpvr.h22 #define HD_PVR_VENDOR_ID 0x2040
23 #define HD_PVR_PRODUCT_ID 0x4900
24 #define HD_PVR_PRODUCT_ID1 0x4901
25 #define HD_PVR_PRODUCT_ID2 0x4902
26 #define HD_PVR_PRODUCT_ID4 0x4903
27 #define HD_PVR_PRODUCT_ID3 0x4982
33 #define HDPVR_FIRMWARE_VERSION 0x08
34 #define HDPVR_FIRMWARE_VERSION_AC3 0x0d
35 #define HDPVR_FIRMWARE_VERSION_0X12 0x12
36 #define HDPVR_FIRMWARE_VERSION_0X15 0x15
[all …]
/linux/drivers/dma/ti/
H A Dk3-psil-j784s4.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Dr3001 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Drs6001 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr4201 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/sound/hda/codecs/realtek/
H A Dalc882.c71 alc_update_coef_idx(codec, 7, 0, 0x2030); in alc889_fixup_coef()
93 static const hda_nid_t conn1[] = { 0x0c, 0x0d }; in alc889_fixup_dac_route()
94 static const hda_nid_t conn2[] = { 0x0e, 0x0f }; in alc889_fixup_dac_route()
95 snd_hda_override_conn_list(codec, 0x14, ARRAY_SIZE(conn1), conn1); in alc889_fixup_dac_route()
96 snd_hda_override_conn_list(codec, 0x15, ARRAY_SIZE(conn1), conn1); in alc889_fixup_dac_route()
97 snd_hda_override_conn_list(codec, 0x18, ARRAY_SIZE(conn2), conn2); in alc889_fixup_dac_route()
98 snd_hda_override_conn_list(codec, 0x1a, ARRAY_SIZE(conn2), conn2); in alc889_fixup_dac_route()
101 static const hda_nid_t conn[] = { 0x0c, 0x0d, 0x0e, 0x0f, 0x26 }; in alc889_fixup_dac_route()
102 snd_hda_override_conn_list(codec, 0x14, ARRAY_SIZE(conn), conn); in alc889_fixup_dac_route()
103 snd_hda_override_conn_list(codec, 0x15, ARRAY_SIZE(conn), conn); in alc889_fixup_dac_route()
[all …]
H A Dalc269.c52 static const hda_nid_t alc269_ignore[] = { 0x1d, 0 }; in alc269_parse_auto_config()
53 static const hda_nid_t alc269_ssids[] = { 0, 0x1b, 0x14, 0x21 }; in alc269_parse_auto_config()
54 static const hda_nid_t alc269va_ssids[] = { 0x15, 0x1b, 0x14, 0 }; in alc269_parse_auto_config()
[all...]
/linux/drivers/media/i2c/
H A Dov02c10.c21 #define OV02C10_REG_CHIP_ID CCI_REG16(0x300a)
22 #define OV02C10_CHIP_ID 0x5602
24 #define OV02C10_REG_STREAM_CONTROL CCI_REG8(0x0100)
26 #define OV02C10_REG_HTS CCI_REG16(0x380c)
29 #define OV02C10_REG_VTS CCI_REG16(0x380e)
30 #define OV02C10_VTS_MAX 0xffff
33 #define OV02C10_REG_EXPOSURE CCI_REG16(0x3501)
39 #define OV02C10_REG_ANALOG_GAIN CCI_REG16(0x3508)
40 #define OV02C10_ANAL_GAIN_MIN 0x10
41 #define OV02C10_ANAL_GAIN_MAX 0xf8
[all …]
/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_core.c42 #define AVL_PCIE_IENR 0x50
43 #define AVL_PCIE_ISR 0x40
44 #define AVL_IRQ_ENABLE 0x80
45 #define AVL_IRQ_ASSERTED 0x80
47 #define GPIO_REG_IO 0x4880
48 #define GPIO_REG_IO_TOGGLE 0x4882
49 #define GPIO_REG_IO_SET 0x4884
50 #define GPIO_REG_IO_CLEAR 0x4886
52 #define GPIO_FEA_RESET (1 << 0)
59 #define NETUP_DMA0_ADDR 0x4900
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.c77 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
126 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) in intel_uncore_forcewake_domain_to_str()
148 fw_clear(d, 0xefff); in fw_domain_reset()
150 fw_clear(d, 0xffff); in fw_domain_reset()
178 return __wait_for_ack(d, ack, 0); in wait_ack_clear()
194 if (fw_ack(d) == ~0) { in fw_domain_wait_ack_clear()
196 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n", in fw_domain_wait_ack_clear()
209 ACK_CLEAR = 0,
218 const u32 value = type == ACK_SET ? ack_bit : 0; in fw_domain_wait_ack_with_fallback()
251 "%s had to use fallback to %s ack, 0x%x (passes %u)\n", in fw_domain_wait_ack_with_fallback()
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
392 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
397 base = of_iomap(np, 0); in imx7d_clocks_init()
401 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
402 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz_common.c39 #define MIB_COUNTER_NUM 0x20
118 { 0x00, "rx" },
119 { 0x01, "rx_hi" },
120 { 0x02, "rx_undersize" },
121 { 0x03, "rx_fragments" },
122 { 0x04, "rx_oversize" },
123 { 0x05, "rx_jabbers" },
124 { 0x06, "rx_symbol_err" },
125 { 0x07, "rx_crc_err" },
126 { 0x08, "rx_align_err" },
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da2xx.xml11 <value name="DITHER_PIXEL" value="0"/>
16 <value name="COLORX_4_4_4_4" value="0"/>
34 <value name="FMT_1_REVERSE" value="0"/>
91 <value name="POSITION_1_VECTOR" value="0"/>
102 <value name="CENTROIDS_ONLY" value="0"/>
108 <value name="DXCLIP_OPENGL" value="0"/>
113 <value name="POLY_DISABLED" value="0"/>
118 <value name="EDRAM_NOP" value="0"/>
125 <value name="LITTLE" value="0"/>
130 <value name="NEVER" value="0"/>
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcudbg_lib.c20 {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
21 {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
22 {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
23 {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
24 {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
25 {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
26 {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
27 {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
28 {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
29 {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
[all …]

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