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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs-fabric.dtsi7 reg = <0x0 0x41000000 0x0 0xF0>;
8 microchip,sync-update-mask = /bits/ 32 <0>;
16 reg = <0x0 0x44000000 0x0 0x1000>;
18 #size-cells = <0>;
28 #clock-cells = <0>;
34 #clock-cells = <0>;
H A Dmpfs-beaglev-fire-fabric.dtsi6 #clock-cells = <0>;
12 #clock-cells = <0>;
20 ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
21 <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
22 <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
23 <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
24 <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
28 reg = <0x0 0x41100000 0x0 0x1000>;
41 reg = <0x0 0x41200000 0x0 0x1000>;
55 reg = <0x0 0x44000000 0x0 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dmarvell,pxa2xx-lcdc.txt26 reg = <0x44000000 0x10000>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drenesas,rzn1-gmac.yaml50 reg = <0x44000000 0x2000>;
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
39 reg = <0xb4000000 0x1000>;
49 ranges = <0xb0000000 0xb0000000 0x10000000
[all …]
H A Dstih407-family.dtsi22 reg = <0x45000000 0x00400000>;
28 reg = <0x44000000 0x01000000>;
35 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0>;
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx95.dtsi23 #size-cells = <0>;
25 A55_0: cpu@0 {
28 reg = <0x0>;
45 reg = <0x100>;
62 reg = <0x200>;
79 reg = <0x300>;
96 reg = <0x400>;
113 reg = <0x500>;
227 #clock-cells = <0>;
228 clock-frequency = <0>;
[all …]
H A Dimx93.dtsi49 #size-cells = <0>;
56 arm,psci-suspend-param = <0x0010033>;
65 A55_0: cpu@0 {
68 reg = <0x0>;
84 reg = <0x100>;
129 #clock-cells = <0>;
136 #clock-cells = <0>;
143 #clock-cells = <0>;
171 reg = <0 0x48000000 0 0x10000>,
172 <0 0x48040000 0 0xc0000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
74 clock-frequency = <0>;
80 reg = <0x40000000 0x04000000>;
90 reg = <0x44000000 0x04000000>;
100 reg = <0x4e000000 0x10000>;
110 reg = <0x4f000000 0x20000>;
[all …]
H A Dvexpress-v2m.dtsi27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 reg = <0x40000000 0x04000000>;
105 reg = <0x44000000 0x04000000>;
115 reg = <0x4e000000 0x10000>;
[all …]
H A Darm-realview-pb11mp.dts45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
53 #size-cells = <0>;
56 MP11_0: cpu@0 {
59 reg = <0>;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
97 reg = <0x1f002000 0x1000>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DHexagon.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
56 defaultMaxPageSize = 0x10000; in Hexagon()
71 return ret.value_or(/* Default Arch Rev: */ 0x60); in calcEFlags()
75 uint32_t result = 0; in applyMask()
76 size_t off = 0; in applyMask()
78 for (size_t bit = 0; bit != 32; ++bit) { in applyMask()
170 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f},
171 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80},
172 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0},
173 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0},
[all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/LoongArch/
H A DEmulateInstructionLoongArch.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 {0xfc000000, 0x40000000, &EmulateInstructionLoongArch::EmulateBEQZ, in GetOpcodeForInstruction()
41 {0xfc000000, 0x44000000, &EmulateInstructionLoongArch::EmulateBNEZ, in GetOpcodeForInstruction()
43 {0xfc000300, 0x48000000, &EmulateInstructionLoongArch::EmulateBCEQZ, in GetOpcodeForInstruction()
45 {0xfc000300, 0x48000100, &EmulateInstructionLoongArch::EmulateBCNEZ, in GetOpcodeForInstruction()
47 {0xfc000000, 0x4c000000, &EmulateInstructionLoongArch::EmulateJIRL, in GetOpcodeForInstruction()
49 {0xfc000000, 0x50000000, &EmulateInstructionLoongArch::EmulateB, in GetOpcodeForInstruction()
51 {0xfc000000, 0x54000000, &EmulateInstructionLoongArch::EmulateBL, in GetOpcodeForInstruction()
53 {0xfc000000, 0x58000000, &EmulateInstructionLoongArch::EmulateBEQ, in GetOpcodeForInstruction()
55 {0xfc000000, 0x5c000000, &EmulateInstructionLoongArch::EmulateBNE, in GetOpcodeForInstruction()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddm816x.dtsi27 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
61 reg = <0x44000000 0x10000>;
69 reg = <0x48180000 0x4000>;
72 ranges = <0 0x48180000 0x4000>;
76 #size-cells = <0>;
85 reg = <0x48140000 0x21000>;
89 ranges = <0 0x48140000 0x21000>;
93 reg = <0x800 0x50a>;
[all …]
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Dam4372.dtsi20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
77 opp-supported-hw = <0xFF 0x01>;
85 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
99 opp-supported-hw = <0xFF 0x10>;
106 opp-supported-hw = <0xFF 0x20>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
/freebsd/sys/arm/include/
H A Darmreg.h44 #define PSR_MODE 0x0000001f /* mode mask */
45 #define PSR_USR32_MODE 0x00000010
46 #define PSR_FIQ32_MODE 0x00000011
47 #define PSR_IRQ32_MODE 0x00000012
48 #define PSR_SVC32_MODE 0x00000013
49 #define PSR_MON32_MODE 0x00000016
50 #define PSR_ABT32_MODE 0x00000017
51 #define PSR_HYP32_MODE 0x0000001a
52 #define PSR_UND32_MODE 0x0000001b
53 #define PSR_SYS32_MODE 0x0000001
[all...]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h49 0x00000001, 0x00000002, 0x00000004, 0x00000008,
50 0x00000010, 0x00000020, 0x00000040, 0x00000080,
51 0x0000001b, 0x00000036
57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
59 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/davinci/
H A Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/st/
H A Dstm32mp251.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
38 arm,smc-id = <0xb200005a>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
67 #size-cells = <0>;
68 linaro,optee-channel-id = <0>;
71 reg = <0x14>;
[all …]

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