Home
last modified time | relevance | path

Searched +full:0 +full:x4300 (Results 1 – 25 of 51) sorted by relevance

123

/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
H A Dqcom-pm8008-regulator.c22 #define LDO_STEPPER_CTL_REG 0x3b
23 #define STEP_RATE_MASK GENMASK(1, 0)
25 #define LDO_VSET_LB_REG 0x40
27 #define LDO_ENABLE_REG 0x46
45 REGULATOR_LINEAR_RANGE(528000, 0, 122, 8000),
49 REGULATOR_LINEAR_RANGE(1504000, 0, 237, 8000),
53 { "ldo1", "vdd-l1-l2", 0x4000, 225000, nldo_ranges, },
54 { "ldo2", "vdd-l1-l2", 0x4100, 225000, nldo_ranges, },
55 { "ldo3", "vdd-l3-l4", 0x4200, 300000, pldo_ranges, },
56 { "ldo4", "vdd-l3-l4", 0x4300, 300000, pldo_ranges, },
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72x.dtsi27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
H A Ddra74x.dtsi49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
/linux/drivers/dma/ti/
H A Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
H A Dk3-psil-am62a.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-am62.c73 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
74 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
78 PSIL_PDMA_XY_PKT(0x4300),
79 PSIL_PDMA_XY_PKT(0x4301),
80 PSIL_PDMA_XY_PKT(0x4302),
81 PSIL_PDMA_XY_PKT(0x4303),
82 PSIL_PDMA_XY_PKT(0x4304),
83 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-am64.c66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
H A Dk3-psil-am62p.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
/linux/include/uapi/linux/
H A Dptrace.h11 #define PTRACE_TRACEME 0
27 /* 0x4200-0x4300 are reserved for architecture-independent additions. */
28 #define PTRACE_SETOPTIONS 0x4200
29 #define PTRACE_GETEVENTMSG 0x4201
30 #define PTRACE_GETSIGINFO 0x4202
31 #define PTRACE_SETSIGINFO 0x4203
50 #define PTRACE_GETREGSET 0x4204
51 #define PTRACE_SETREGSET 0x4205
53 #define PTRACE_SEIZE 0x4206
54 #define PTRACE_INTERRUPT 0x4207
[all …]
/linux/arch/powerpc/include/asm/
H A Ddcr-regs.h29 #define DCRN_CPR0_CONFIG_ADDR 0xc
30 #define DCRN_CPR0_CONFIG_DATA 0xd
33 #define DCRN_SDR0_CONFIG_ADDR 0xe
34 #define DCRN_SDR0_CONFIG_DATA 0xf
36 #define SDR0_PFC0 0x4100
37 #define SDR0_PFC1 0x4101
38 #define SDR0_PFC1_EPS 0x1c00000
40 #define SDR0_PFC1_RMII 0x02000000
41 #define SDR0_MFR 0x4300
42 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
[all …]
/linux/drivers/video/fbdev/
H A Dbroadsheetfb.c68 .sdcfg = (67 | (0 << 8) | (0 << 9) | (0 << 10) | (0 << 12)),
71 .fsynclen = 0,
80 .sdcfg = (100 | (1 << 8) | (1 << 9) | (0 << 10) | (0 << 12)),
83 .fsynclen = 0,
98 .xpanstep = 0,
99 .ypanstep = 0,
100 .ywrapstep = 0,
112 .red = { 0, 4, 0 },
113 .green = { 0, 4, 0 },
114 .blue = { 0, 4, 0 },
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr3001 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Drs6001 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr4201 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dti,icssg-prueth.yaml21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
35 - const: tx0-0
39 - const: tx1-0
92 const: 0
95 ^port@[0-1]$:
104 - enum: [0, 1]
131 - port@0
170 /* Example k3-am654 base board SR2.0, dual-emac */
174 pinctrl-0 = <&icssg2_rgmii_pins_default>;
191 dmas = <&main_udmap 0xc300>, /* egress slice 0 */
[all …]
/linux/drivers/media/usb/gspca/
H A Dstk1135.c51 if (gspca_dev->usb_err < 0) in reg_r()
52 return 0; in reg_r()
53 ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), in reg_r()
54 0x00, in reg_r()
56 0x00, in reg_r()
61 gspca_dbg(gspca_dev, D_USBI, "reg_r 0x%x=0x%02x\n", in reg_r()
62 index, gspca_dev->usb_buf[0]); in reg_r()
63 if (ret < 0) { in reg_r()
64 pr_err("reg_r 0x%x err %d\n", index, ret); in reg_r()
66 return 0; in reg_r()
[all …]
/linux/include/sound/
H A Dcs48l32_registers.h13 #define CS48L32_DEVID 0x0
14 #define CS48L32_REVID 0x4
15 #define CS48L32_OTPID 0x10
16 #define CS48L32_SFT_RESET 0x20
17 #define CS48L32_CTRL_IF_DEBUG3 0xA8
18 #define CS48L32_MCU_CTRL1 0x804
19 #define CS48L32_GPIO1_CTRL1 0xc08
20 #define CS48L32_GPIO3_CTRL1 0xc10
21 #define CS48L32_GPIO7_CTRL1 0xc20
22 #define CS48L32_GPIO16_CTRL1 0xc44
[all …]
/linux/drivers/ssb/
H A Dscan.c101 u16 chipid_fallback = 0; in pcidev_to_chipid()
104 case 0x4301: in pcidev_to_chipid()
105 chipid_fallback = 0x4301; in pcidev_to_chipid()
107 case 0x4305 ... 0x4307: in pcidev_to_chipid()
108 chipid_fallback = 0x4307; in pcidev_to_chipid()
110 case 0x4403: in pcidev_to_chipid()
111 chipid_fallback = 0x4402; in pcidev_to_chipid()
113 case 0x4610 ... 0x4615: in pcidev_to_chipid()
114 chipid_fallback = 0x4610; in pcidev_to_chipid()
116 case 0x4710 ... 0x4715: in pcidev_to_chipid()
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx8mn.c334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
352 …hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe()
353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
355 …hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
H A Dclk-imx8mm.c313 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
322 base = of_iomap(np, 0); in imx8mm_clocks_probe()
327 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
328 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
329 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
330 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
331 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
332 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
333 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
334 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dusb.c29 #define BRCMF_POSTBOOT_ID 0xA123 /* ID to detect if dongle
34 #define BRCMF_USB_CBCTL_WRITE 0
45 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
46 BRCMF_FW_ENTRY(BRCM_CC_43235_CHIP_ID, 0x00000008, 43236B),
47 BRCMF_FW_ENTRY(BRCM_CC_43236_CHIP_ID, 0x00000008, 43236B),
48 BRCMF_FW_ENTRY(BRCM_CC_43238_CHIP_ID, 0x00000008, 43236B),
49 BRCMF_FW_ENTRY(BRCM_CC_43242_CHIP_ID, 0xFFFFFFFF, 43242A),
50 BRCMF_FW_ENTRY(BRCM_CC_43566_CHIP_ID, 0xFFFFFFFF, 43569),
51 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43569),
52 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373)
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/pci/controller/
H A Dpcie-brcmstb.c44 #define BRCM_PCIE_CAP_REGS 0x00ac
47 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
48 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
49 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
51 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
52 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
54 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
55 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x1f0
57 #define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
58 #define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
[all …]

123