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/linux/Documentation/devicetree/bindings/i2c/
H A Drenesas,rmobile-iic.yaml139 reg = <0xe6500000 0x425>;
143 dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>;
148 #size-cells = <0>;
H A Di2c-demux-pinctrl.yaml68 #size-cells = <0>;
80 reg = <0xe6520000 0x425>;
81 pinctrl-0 = <&iic2_pins>;
95 reg = <0 0xe6530000 0 0x40>;
96 pinctrl-0 = <&i2c2_pins>;
116 #size-cells = <0>;
120 #sound-dai-cells = <0>;
121 reg = <0x12>;
126 reg = <0x20>;
138 reg = <0x39>;
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7792.dtsi40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
92 ranges = <0 0 0 0x1c000000>;
105 #clock-cells = <0>;
[all …]
/linux/drivers/media/dvb-frontends/
H A Dau8522_priv.h27 #define AU8522_ANALOG_MODE 0
88 #define AU8522_INPUT_CONTROL_REG081H 0x081
89 #define AU8522_PGA_CONTROL_REG082H 0x082
90 #define AU8522_CLAMPING_CONTROL_REG083H 0x083
92 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3
93 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4
94 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5
95 #define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6
96 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7
97 #define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lcn.c66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup()
67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup()
70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup()
71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup()
72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup()
73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup()
74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup()
75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup()
76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup()
77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_lcn.c40 #define NOISE_IF_OFF 0
45 #define PAPD2LUT 0
46 #define PAPD_CORR_NORM 0
47 #define PAPD_BLANKING_THRESHOLD 0
48 #define PAPD_STOP_AFTER_LAST_UPDATE 0
70 (0 + 8)
72 (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
75 (0 + 8)
77 (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
85 (read_phy_reg((pi), 0x451) & \
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/drivers/mfd/
H A Dcs47l92-tables.c21 { 0x3A2, 0x2C29 },
22 { 0x3A3, 0x0E00 },
23 { 0x281, 0x0000 },
24 { 0x282, 0x0000 },
25 { 0x4EA, 0x0100 },
26 { 0x22B, 0x0000 },
27 { 0x4A0, 0x0080 },
28 { 0x4A1, 0x0000 },
29 { 0x4A2, 0x0000 },
30 { 0x180B, 0x033F },
[all …]
H A Dcs47l90-tables.c18 { 0x8A, 0x5555 },
19 { 0x8A, 0xAAAA },
20 { 0x4CF, 0x0700 },
21 { 0x171, 0x0003 },
22 { 0x101, 0x0444 },
23 { 0x159, 0x0002 },
24 { 0x120, 0x0444 },
25 { 0x1D1, 0x0004 },
26 { 0x1E0, 0xC084 },
27 { 0x159, 0x0000 },
[all …]
H A Dcs47l85-tables.c18 { 0x80, 0x0003 },
19 { 0x213, 0x03E4 },
20 { 0x177, 0x0281 },
21 { 0x197, 0x0281 },
22 { 0x1B7, 0x0281 },
23 { 0x4B1, 0x010A },
24 { 0x4CF, 0x0933 },
25 { 0x36C, 0x011B },
26 { 0x4B8, 0x1120 },
27 { 0x4A0, 0x3280 },
[all …]
/linux/include/linux/mfd/arizona/
H A Dregisters.h16 #define ARIZONA_SOFTWARE_RESET 0x00
17 #define ARIZONA_DEVICE_REVISION 0x01
18 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
19 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
20 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
21 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
22 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
23 #define ARIZONA_CTRL_IF_STATUS_1 0x0D
24 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
25 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]