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/linux/Documentation/devicetree/bindings/net/
H A Dti,icssg-prueth.yaml21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
35 - const: tx0-0
39 - const: tx1-0
92 const: 0
95 ^port@[0-1]$:
104 - enum: [0, 1]
131 - port@0
170 /* Example k3-am654 base board SR2.0, dual-emac */
174 pinctrl-0 = <&icssg2_rgmii_pins_default>;
191 dmas = <&main_udmap 0xc300>, /* egress slice 0 */
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr520.c41 for (i = 0; i < rdev->usec_timeout; i++) { in r520_mc_wait_for_idle()
45 return 0; in r520_mc_wait_for_idle()
58 * DST_PIPE_CONFIG 0x170C in r520_gpu_init()
59 * GB_TILE_CONFIG 0x4018 in r520_gpu_init()
60 * GB_FIFO_SIZE 0x4024 in r520_gpu_init()
61 * GB_PIPE_SELECT 0x402C in r520_gpu_init()
62 * GB_PIPE_SELECT2 0x4124 in r520_gpu_init()
63 * Z_PIPE_SHIFT 0 in r520_gpu_init()
64 * Z_PIPE_MASK 0x000000003 in r520_gpu_init()
65 * GB_FIFO_SIZE2 0x4128 in r520_gpu_init()
[all …]
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
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/linux/drivers/phy/cadence/
H A Dphy-cadence-salvo.c19 #define USB3_PHY_OFFSET 0x0
20 #define USB2_PHY_OFFSET 0x38000
22 #define PHY_PMA_CMN_CTRL1 0xC800
23 #define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
24 #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
25 #define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
26 #define TB_ADDR_CMN_PLL0_INTDIV 0x0094
27 #define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
28 #define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
29 #define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
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/linux/drivers/pinctrl/
H A Dpinctrl-rp1.c27 #define RP1_INT_EDGE_FALLING BIT(0)
31 #define RP1_INT_MASK GENMASK(3, 0)
37 #define RP1_FSEL_ALT0 0x00
38 #define RP1_FSEL_GPIO 0x05
39 #define RP1_FSEL_NONE 0x09
40 #define RP1_FSEL_NONE_HW 0x1f
42 #define RP1_PAD_DRIVE_2MA 0x0
43 #define RP1_PAD_DRIVE_4MA 0x1
44 #define RP1_PAD_DRIVE_8MA 0x2
45 #define RP1_PAD_DRIVE_12MA 0x3
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/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/net/ethernet/sun/
H A Dcassini.h8 * vendor id: 0x108E (Sun Microsystems, Inc.)
9 * device id: 0xabba (Cassini)
10 * revision ids: 0x01 = Cassini
11 * 0x02 = Cassini rev 2
12 * 0x10 = Cassini+
13 * 0x11 = Cassini+ 0.2u
15 * vendor id: 0x100b (National Semiconductor)
16 * device id: 0x0035 (DP83065/Saturn)
17 * revision ids: 0x30 = Saturn B2
19 * rings are all offset from 0.
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b_table.c10 {0x704, 0x601E0500},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x47BC, 0x00000380},
18 {0x4018, 0x4F4C084B},
19 {0x401C, 0x084A4E52},
[all …]
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x4018, 0x4F4C084B},
18 {0x401C, 0x084A4E52},
19 {0x4020, 0x4D504E4B},
[all …]
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
18 {0x4004, 0xCA014000},
19 {0x4008, 0xC751D4F0},
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]