Searched +full:0 +full:x40088000 (Results 1 – 4 of 4) sorted by relevance
| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | nxp,lpc1850-gpio.yaml | 45 0..9 range, for GPIO pin interrupts it is equal
68 reg = <0x400f4000 0x4000>, <0x40087000 0x1000>,
69 <0x40088000 0x1000>, <0x40089000 0x1000>;
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| /linux/arch/arm/boot/dts/nxp/lpc/ |
| H A D | lpc32xx.dtsi | 20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
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| /linux/arch/arm/mach-lpc32xx/ |
| H A D | lpc32xx.h | 17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x51",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0x48",
18 "UMask": "0x2"
22 "Counter": "0,1,2,3",
23 "EventCode": "0x48",
27 "UMask": "0x1"
31 "Counter": "0,1,2,3",
[all …]
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