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/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml169 reg = <0x5800a000 0x2000>;
183 st,syscon = <&syscfg 0x4>;
194 reg = <0x40028000 0x8000>;
196 interrupts = <0 61 0>, <0 62 0>;
199 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
200 st,syscon = <&syscfg 0x4>;
210 reg = <0x40028000 0x8000>;
216 st,syscon = <&syscfg 0x4>;
/linux/arch/arm/include/debug/
H A Dvf.S6 #define VF_UART0_BASE_ADDR 0x40027000
7 #define VF_UART1_BASE_ADDR 0x40028000
8 #define VF_UART2_BASE_ADDR 0x40029000
9 #define VF_UART3_BASE_ADDR 0x4002a000
14 #define VF_UART_VIRTUAL_BASE 0xfe000000
18 and \rv, \rp, #0xffffff @ offset within 16MB section
23 strb \rd, [\rx, #0x7] @ Data Register
27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
/linux/Documentation/devicetree/bindings/gpio/
H A Dnxp,lpc3220-gpio.yaml25 0: GPIO P0
33 - bit 0 specifies polarity (0 for normal, 1 for inverted)
47 reg = <0x40028000 0x1000>;
/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dcache.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x51",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0x48",
18 "UMask": "0x2"
22 "Counter": "0,1,2,3",
23 "EventCode": "0x48",
27 "UMask": "0x1"
31 "Counter": "0,1,2,3",
[all …]