Home
last modified time | relevance | path

Searched +full:0 +full:x40000f20 (Results 1 – 19 of 19) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie-sa8775p.yaml101 reg = <0x0 0x01c00000 0x0 0x3000>,
102 <0x0 0x40000000 0x0 0xf20>,
103 <0x0 0x40000f20 0x0 0xa8>,
104 <0x0 0x40001000 0x0 0x4000>,
105 <0x0 0x40100000 0x0 0x100000>,
106 <0x0 0x01c03000 0x0 0x1000>;
108 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
109 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
111 bus-range = <0x00 0xff>;
113 linux,pci-domain = <0>;
[all …]
H A Dqcom,pcie-sc7280.yaml97 reg = <0 0x01c08000 0 0x3000>,
98 <0 0x40000000 0 0xf1d>,
99 <0 0x40000f20 0 0xa8>,
100 <0 0x40001000 0 0x1000>,
101 <0 0x40100000 0 0x100000>;
103 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
104 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
106 bus-range = <0x00 0xff>;
159 interrupt-map-mask = <0 0 0 0x7>;
160 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dqcom,pcie-ep.yaml295 reg = <0x01c00000 0x3000>,
296 <0x40000000 0xf1d>,
297 <0x40000f20 0xc8>,
298 <0x40001000 0x1000>,
299 <0x40002000 0x1000>,
300 <0x01c03000 0x3000>;
314 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
331 linux,pci-domain = <0>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsa8540p.dtsi184 linux,pci-domain = <0>;
201 reg = <0x0 0x01c10000 0x0 0x3000>,
202 <0x0 0x40000000 0x0 0xf1d>,
203 <0x0 0x40000f20 0x0 0xa8>,
204 <0x0 0x40001000 0x0 0x1000>,
205 <0x0 0x40100000 0x0 0x100000>;
208 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
216 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dipq5424.dtsi23 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0>;
60 reg = <0x100>;
75 reg = <0x200>;
90 reg = <0x300>;
105 qcom,dload-mode = <&tcsr 0x25100>;
112 reg = <0x0 0x80000000 0x0 0x0>;
[all …]
H A Dsar2130p.dtsi34 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsa8775p.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
H A Dsm8550.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
[all …]
H A Dsc7280.dtsi83 #clock-cells = <0>;
89 #clock-cells = <0>;
100 reg = <0x0 0x004cd000 0x0 0x1000>;
104 reg = <0x0 0x80000000 0x0 0x600000>;
109 reg = <0x0 0x80600000 0x0 0x200000>;
114 reg = <0x0 0x80800000 0x0 0x60000>;
119 reg = <0x0 0x80860000 0x0 0x20000>;
125 reg = <0x0 0x80884000 0x0 0x10000>;
130 reg = <0x0 0x808ff000 0x0 0x1000>;
135 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
H A Dqcom-ipq4019.dtsi21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
45 #size-cells = <0>;
46 cpu@0 {
53 reg = <0x0>;
55 clock-frequency = <0>;
66 reg = <0x1>;
68 clock-frequency = <0>;
[all …]
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]