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/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x0000000
[all...]
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x4451147
[all...]
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x0000000
[all...]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D9
[all...]
H A Drtw8822b_table.c10 0x029, 0x000000F9,
11 0x420, 0x00000080,
12 0x421, 0x0000001F,
13 0x428, 0x0000000A,
14 0x429, 0x00000010,
15 0x430, 0x00000000,
16 0x431, 0x00000000,
17 0x432, 0x00000000,
18 0x433, 0x00000001,
19 0x434, 0x00000004,
[all …]
H A Drtw8821c_table.c10 0x010, 0x00000043,
11 0x025, 0x0000001D,
12 0x026, 0x000000CE,
13 0x04F, 0x00000001,
14 0x029, 0x000000F
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls2088a.dtsi23 cpu0: cpu@0 {
26 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
36 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
46 reg = <0x100>;
56 reg = <0x101>;
66 reg = <0x200>;
76 reg = <0x201>;
86 reg = <0x300>;
[all …]
H A Dfsl-ls2080a.dtsi23 cpu0: cpu@0 {
26 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
36 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
46 reg = <0x100>;
56 reg = <0x101>;
66 reg = <0x200>;
76 reg = <0x201>;
86 reg = <0x300>;
[all …]
H A Dimx8mm-data-modul-edm-sbc.dts28 reg = <0x0 0x40000000 0 0x40000000>;
34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
38 pwms = <&pwm1 0 5000000 0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
65 pinctrl-0 = <&pinctrl_panel_vcc_reg>;
69 gpio = <&gpio3 6 0>;
78 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/loongson/
H A Drs780e-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000
9 0 0x40000000 0 0x40000000 0 0x40000000
10 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
18 reg = <0 0x1a000000 0 0x02000000>;
20 ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
21 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
28 ranges = <1 0 0 0x18000000 0x4000>;
32 reg = <1 0x70 0x8>;
39 reg = <1 0x800 0x100>;
H A Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
H A Dloongson64-2k1000.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0x0>;
27 #clock-cells = <0>;
33 #address-cells = <0>;
43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
44 0 0x40000000 0 0x40000000 0 0x40000000
45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
51 ranges = <1 0x0 0x0 0x18000000 0x4000>;
56 reg = <0 0x1fe07000 0 0x422>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm97435svmb.dts11 memory@0 {
13 reg = <0x00000000 0x10000000>,
14 <0x20000000 0x30000000>,
15 <0x90000000 0x40000000>;
135 brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
136 dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
137 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
138 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
H A Dbcm97425svmb.dts11 memory@0 {
13 reg = <0x00000000 0x10000000>,
14 <0x20000000 0x30000000>,
15 <0x90000000 0x40000000>;
119 flash@0 {
121 reg = <0>;
133 flash0.cfe@0 {
134 reg = <0x0 0x200000>;
138 reg = <0x200000 0x40000>;
142 reg = <0x240000 0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm7445-bcm97445svmb.dts9 memory@0 {
11 reg = <0x00 0x00000000 0x00 0x40000000>,
12 <0x00 0x40000000 0x00 0x40000000>,
13 <0x00 0x80000000 0x00 0x40000000>;
30 flash1.rootfs0@0 {
31 reg = <0x0 0x0 0x0 0x80000000>;
35 reg = <0x0 0x80000000 0x0 0x80000000>;
/freebsd/sys/contrib/ncsw/Peripherals/FM/Pcd/
H A Dfm_plcr.h49 #define FM_PCD_PLCR_PAR_GO 0x80000000
50 #define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF
51 #define FM_PCD_PLCR_PAR_R 0x40000000
57 #define FM_PCD_PLCR_PEMODE_PI 0x80000000
58 #define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
59 #define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
60 #define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
61 #define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
62 #define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
63 #define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-rcar-gen2.txt42 defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
50 reg = <0x0 0xee090000 0x0 0xc00>,
51 <0x0 0xee080000 0x0 0x1100>;
52 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
55 bus-range = <0 0>;
59 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
60 interrupt-map-mask = <0xff00 0 0 0x7>;
61 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
62 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
63 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
[all …]
H A Drcar-pci.txt55 reg = <0 0xfe000000 0 0x80000>;
58 bus-range = <0x00 0xff>;
60 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
61 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
62 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
63 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
64 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
65 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
66 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
68 interrupt-map-mask = <0 0 0 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a77950-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
H A Dr8a77951-salvator-xs.dts3 * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dr8a77951-salvator-x.dts3 * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dr8a77951-ulcb.dts3 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES2.0+
20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
48 clock-names = "du.0", "du.1", "du.2", "du.3",
49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
H A Dr8a77950-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k0500.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0>;
29 #clock-cells = <0>;
44 thermal-sensors = <&tsensor 0>;
64 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
65 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
66 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
67 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
68 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_kg.h81 uint32_t kgse_dv0; /**< KeyGen Scheme Entry Default Value 0 */
99 #define FM_KG_KGAR_GO 0x80000000
100 #define FM_KG_KGAR_READ 0x40000000
101 #define FM_KG_KGAR_WRITE 0x00000000
102 #define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000
103 #define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000
105 #define KG_SCH_PP_SHIFT_HIGH 0x80000000
106 #define KG_SCH_PP_NO_GEN 0x10000000
107 #define KG_SCH_PP_SHIFT_LOW 0x0000F000
108 #define KG_SCH_MODE_NIA_PLCR 0x40000000
[all …]

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