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/linux/arch/arm/mach-omap2/
H A Dfb.c32 DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
33 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
34 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
35 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
36 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
40 DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
41 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
42 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
43 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
44 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dti,am654-hbmc.yaml31 "^flash@[0-1],[0-9a-f]+$":
54 reg = <0x0 0x47034000 0x0 0x100>,
55 <0x5 0x00000000 0x1 0x0000000>;
56 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
57 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
58 clocks = <&k3_clks 102 0>;
62 mux-controls = <&hbmc_mux 0>;
64 flash@0,0 {
66 reg = <0x0 0x0 0x4000000>;
H A Dmxicy,nand-ecc-engine.yaml36 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
38 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
41 #size-cells = <0>;
43 flash@0 {
45 reg = <0>;
52 reg = <0x43c40000 0x10000>;
59 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
61 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
64 #size-cells = <0>;
67 flash@0 {
[all …]
/linux/arch/arm/boot/compressed/
H A Dmisc.c16 * which should point to addresses in RAM and cleared to 0 on start.
40 int status, i = 0x4000000; in icedcc_putc()
43 if (--i < 0) in icedcc_putc()
46 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status)); in icedcc_putc()
49 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); in icedcc_putc()
57 int status, i = 0x4000000; in icedcc_putc()
60 if (--i < 0) in icedcc_putc()
63 asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); in icedcc_putc()
66 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); in icedcc_putc()
73 int status, i = 0x4000000; in icedcc_putc()
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv1800b.dtsi17 reg = <0x80000000 0x4000000>;
26 reg = <0x03001000 0x1000>,
27 <0x05027000 0x1000>;
33 reg = <0x03002000 0x1000>;
40 reg = <0x70000000 0x4000000>;
43 #address-cells = <0>;
50 reg = <0x74000000 0x10000>;
/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-lmu5000.dts20 reg = <0x20000000 0x4000000>;
28 main_clock: clock@0 {
43 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
48 reg = <0x3 0x0 0x800000>;
62 kernel@0 {
64 reg = <0x0 0x400000>;
69 reg = <0x400000 0x3C00000>;
74 reg = <0x4000000 0x2000000>;
79 reg = <0x6000000 0x2000000>;
107 pinctrl-0 = <&pinctrl_ssc0_tx>;
[all …]
/linux/Documentation/core-api/kho/
H A Dfdt.rst53 preserved-memory-map = <0x40be16 0x1000000>;
56 fdt = <0x1517 0x1000000>;
71 start = <0xc06b 0x4000000>;
72 size = <0x04 0x00>;
77 start = <0xc067 0x4000000>;
78 size = <0x04 0x00>;
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-sev-kit.dts35 reg = <0x0 0x80000000 0x0 0x2000000>;
40 reg = <0x0 0xc4000000 0x0 0x4000000>;
45 reg = <0x0 0xd4000000 0x0 0x4000000>;
51 reg = <0x10 0x0 0x0 0x76000000>;
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-mercury5-ssc8336n.dtsi12 reg = <0x20000000 0x4000000>;
H A Dmstar-infinity-msc313.dtsi12 reg = <0x20000000 0x4000000>;
H A Dmstar-infinity3-msc313e.dtsi12 reg = <0x20000000 0x4000000>;
/linux/Documentation/gpu/amdgpu/display/
H A Dtrace-groups-table.csv2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-lschlv2.dts12 reg = <0x00000000 0x4000000>;
/linux/Documentation/devicetree/bindings/regulator/
H A Dti-abb-regulator.txt17 - #address-cells: should be 0
18 - #size-cells: should be 0
32 0-bypass
56 from efuse-address to pick up ABB characteristics. Set to 0 if
60 + efuse maps to RBB mask. Set to 0 to ignore this.
64 Set to 0 to ignore this.
72 #address-cells = <0>;
73 #size-cells = <0>;
74 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
76 ti,tranxdone-status-mask = <0x4000000>;
[all …]

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