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/linux/Documentation/devicetree/bindings/mfd/
H A Dapple,smc.yaml60 reg = <0x2 0x3e400000 0x0 0x4000>,
61 <0x2 0x3fe00000 0x0 0x100000>;
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex_socdk_nand.dts43 reg = <0 0x80000000 0 0>;
60 #size-cells = <0>;
62 phy0: ethernet-phy@0 {
65 txd0-skew-ps = <0>; /* -420ps */
66 txd1-skew-ps = <0>; /* -420ps */
67 txd2-skew-ps = <0>; /* -420ps */
68 txd3-skew-ps = <0>; /* -420ps */
69 rxd0-skew-ps = <420>; /* 0ps */
70 rxd1-skew-ps = <420>; /* 0ps */
71 rxd2-skew-ps = <420>; /* 0ps */
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_socdk_nand.dts44 reg = <0 0x80000000 0 0>;
54 soc@0 {
59 reg = <0xff8c8c00 0x100>;
81 #size-cells = <0>;
83 phy0: ethernet-phy@0 {
86 txd0-skew-ps = <0>; /* -420ps */
87 txd1-skew-ps = <0>; /* -420ps */
88 txd2-skew-ps = <0>; /* -420ps */
89 txd3-skew-ps = <0>; /* -420ps */
90 rxd0-skew-ps = <420>; /* 0ps */
[all …]
/linux/arch/m68k/fpsp040/
H A Dstwotox.S31 | N = 64(M + M') + j, j = 0,1,2,...,63.
44 | N = 64(M + M') + j, j = 0,1,2,...,63.
69 | 1. Generate overflow by Huge * Huge if X > 0; otherwise, generate
88 BOUNDS1: .long 0x3FB98000,0x400D80C0 | ... 2^(-70),16480
89 BOUNDS2: .long 0x3FB98000,0x400B9B07 | ... 2^(-70),16480 LOG2/LOG10
91 L2TEN64: .long 0x406A934F,0x0979A371 | ... 64LOG10/LOG2
92 L10TWO1: .long 0x3F734413,0x509F8000 | ... LOG2/64LOG10
94 L10TWO2: .long 0xBFCD0000,0xC0219DC1,0xDA994FD2,0x00000000
96 LOG10: .long 0x40000000,0x935D8DDD,0xAAA8AC17,0x00000000
98 LOG2: .long 0x3FFE0000,0xB17217F7,0xD1CF79AC,0x00000000
[all …]
/linux/arch/m68k/ifpsp060/
H A Dfpsp.sa1 .long 0x60ff0000,0x17400000,0x60ff0000,0x15f40000
2 .long 0x60ff0000,0x02b60000,0x60ff0000,0x04700000
3 .long 0x60ff0000,0x1b100000,0x60ff0000,0x19aa0000
4 .long 0x60ff0000,0x1b5a0000,0x60ff0000,0x062e0000
5 .long 0x60ff0000,0x102c0000,0x51fc51fc,0x51fc51fc
6 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
7 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
8 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
9 .long 0x2f00203a,0xff2c487b,0x0930ffff,0xfef8202f
10 .long 0x00044e74,0x00042f00,0x203afef2,0x487b0930
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_10_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_2_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux/arch/m68k/ifpsp060/src/
H A Dfplsp.S37 short 0x0000
39 short 0x0000
41 short 0x0000
44 short 0x0000
46 short 0x0000
48 short 0x0000
51 short 0x0000
53 short 0x0000
55 short 0x0000
58 short 0x0000
[all …]
H A Dfpsp.S43 set _off_bsun, 0x00
44 set _off_snan, 0x04
45 set _off_operr, 0x08
46 set _off_ovfl, 0x0c
47 set _off_unfl, 0x10
48 set _off_dz, 0x14
49 set _off_inex, 0x18
50 set _off_fline, 0x1c
51 set _off_fpu_dis, 0x20
52 set _off_trap, 0x24
[all …]