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Searched +full:0 +full:x3fc (Results 1 – 25 of 79) sorted by relevance

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/linux/tools/testing/selftests/bpf/prog_tests/
H A Dalign.c38 BPF_MOV64_IMM(BPF_REG_0, 0),
43 {0, "R1", "ctx()"},
44 {0, "R10", "fp0"},
45 {0, "R3", "2"},
66 BPF_MOV64_IMM(BPF_REG_0, 0),
71 {0, "R1", "ctx()"},
72 {0, "R10", "fp0"},
73 {0, "R3", "1"},
95 BPF_MOV64_IMM(BPF_REG_0, 0),
100 {0, "R
[all...]
/linux/drivers/gpu/drm/radeon/
H A Dvce_v2_0.c45 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
49 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
53 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
56 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
59 tmp |= 0xe7; in vce_v2_0_set_sw_cg()
60 tmp &= ~0xe70000; in vce_v2_0_set_sw_cg()
64 tmp |= 0x1fe000; in vce_v2_0_set_sw_cg()
65 tmp &= ~0xff000000; in vce_v2_0_set_sw_cg()
69 tmp |= 0x3fc; in vce_v2_0_set_sw_cg()
79 tmp &= ~0x00060006; in vce_v2_0_set_dyn_cg()
[all …]
/linux/drivers/input/touchscreen/
H A Dda9052_tsi.c18 #define TSI_PEN_DOWN_STATUS 0x40
30 da9052_reg_update(tsi->da9052, DA9052_TSI_CONT_A_REG, 1 << 0, on); in da9052_ts_adc_toggle()
59 if (ret < 0) in da9052_ts_read()
65 if (ret < 0) in da9052_ts_read()
71 if (ret < 0) in da9052_ts_read()
77 if (ret < 0) in da9052_ts_read()
82 x = ((x << 2) & 0x3fc) | (v & 0x3); in da9052_ts_read()
83 y = ((y << 2) & 0x3fc) | ((v & 0xc) >> 2); in da9052_ts_read()
84 z = ((z << 2) & 0x3fc) | ((v & 0x30) >> 4); in da9052_ts_read()
108 if (ret < 0 || (ret & TSI_PEN_DOWN_STATUS)) { in da9052_ts_pen_work()
[all …]
H A Dda9034-ts.c20 #define DA9034_MANUAL_CTRL 0x50
23 #define DA9034_AUTO_CTRL1 0x51
25 #define DA9034_AUTO_CTRL2 0x52
29 #define DA9034_TSI_CTRL1 0x53
30 #define DA9034_TSI_CTRL2 0x54
31 #define DA9034_TSI_X_MSB 0x6c
32 #define DA9034_TSI_Y_MSB 0x6d
33 #define DA9034_TSI_XY_LSB 0x6e
98 touch->last_x = ((_x << 2) & 0x3fc) | (_v & 0x3); in read_tsi()
99 touch->last_y = ((_y << 2) & 0x3fc) | ((_v & 0xc) >> 2); in read_tsi()
[all …]
/linux/arch/arm/mach-sa1100/
H A Dassabet.c93 gc = gpio_reg_init(NULL, reg, -1, 32, "assabet", 0xff000000, def_val, in assabet_init_gpio()
112 #define RST_UCB1X00 (1 << 0)
141 for (i = 0; i < 8; i++, byte <<= 1) { in adv7171_send()
144 if (byte & 0x80) in adv7171_send()
184 adv7171_send(0x54); in adv7171_write()
198 adv7171_write(0x04, 0x40); in adv7171_sleep()
246 * Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
251 .size = 0x00020000,
252 .offset = 0,
256 .size = 0x00020000,
[all …]
/linux/tools/testing/selftests/bpf/verifier/
H A Djit.c5 BPF_MOV64_IMM(BPF_REG_1, 0xff),
8 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x3fc, 1),
12 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0xff, 1),
15 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x7f, 1),
28 BPF_MOV64_IMM(BPF_REG_1, 0xff),
31 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x3fc, 1),
36 BPF_JMP_IMM(BPF_JEQ, BPF_REG_4, 0xff, 1),
39 BPF_JMP_IMM(BPF_JEQ, BPF_REG_4, 0, 1),
51 BPF_LD_IMM64(BPF_REG_1, 0xfeffffffffffffffULL),
53 BPF_LD_IMM64(BPF_REG_2, 0xfeffffffULL),
[all …]
/linux/arch/arm/mach-omap2/
H A Dam33xx.h11 #define L4_SLOW_AM33XX_BASE 0x48000000
13 #define AM33XX_SCM_BASE 0x44E10000
15 #define AM33XX_PRCM_BASE 0x44E00000
16 #define AM43XX_PRCM_BASE 0x44DF0000
17 #define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC)
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/linux/Documentation/filesystems/ext4/
H A Dmmp.rst42 * - 0x0
45 - Magic number for MMP, 0x004D4D50 (“MMP”).
46 * - 0x4
50 * - 0x8
54 * - 0x10
58 * - 0x50
62 * - 0x70
66 * - 0x72
70 * - 0x74
74 * - 0x3FC
/linux/arch/parisc/include/asm/
H A Dfutex.h17 return (ua >> 2) & 0x3fc; in _futex_hash_index()
48 if (unlikely(get_user(oldval, uaddr) != 0)) { in arch_futex_atomic_op_inuser()
53 ret = 0; in arch_futex_atomic_op_inuser()
77 if (unlikely(put_user(tmp, uaddr) != 0)) in arch_futex_atomic_op_inuser()
111 if (unlikely(get_user(val, uaddr) != 0)) { in futex_atomic_cmpxchg_inatomic()
116 if (val == oldval && unlikely(put_user(newval, uaddr) != 0)) { in futex_atomic_cmpxchg_inatomic()
124 return 0; in futex_atomic_cmpxchg_inatomic()
/linux/include/linux/
H A Dtc.h29 #define TC_OLDCARD 0x3c0000
30 #define TC_NEWCARD 0x000000
32 #define TC_ROM_WIDTH 0x3e0
33 #define TC_ROM_STRIDE 0x3e4
34 #define TC_ROM_SIZE 0x3e8
35 #define TC_SLOT_SIZE 0x3ec
36 #define TC_PATTERN0 0x3f0
37 #define TC_PATTERN1 0x3f4
38 #define TC_PATTERN2 0x3f8
39 #define TC_PATTERN3 0x3fc
[all …]
/linux/arch/arm/mach-mediatek/
H A Dplatsmp.c17 #define MTK_SMP_REG_SIZE 0x1000
27 0x80002000, 0x3fc,
28 { 0x534c4131, 0x4c415332, 0x41534c33 },
29 { 0x3f8, 0x3f8, 0x3f8 },
33 0x10001400, 0x08,
34 { 0x534c4131 },
35 { 0x0c },
39 0x10002000, 0x34,
40 { 0x534c4131, 0x4c415332, 0x41534c33 },
41 { 0x38, 0x3c, 0x40 },
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx94/sys/
H A Dmetrics.json5 …_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_ma…
13 …_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_ma…
21 "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
29 "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
37 "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32",
45 "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32",
51 "BriefDescription": "bytes of a55 core 0 read from ddr",
53 "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
59 "BriefDescription": "bytes of a55 core 0 write to ddr",
61 "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
[all …]
/linux/include/soc/at91/
H A Dsama7-ddr.h15 #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
20 #define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
22 #define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
26 #define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
27 #define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
32 #define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
37 #define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgddr3.c35 while (xlat->id >= 0) { in ramxlat()
45 { 5, 5 }, { 7, 7 }, { 8, 0 }, { 9, 1 }, { 10, 2 }, { 11, 3 }, { 12, 8 },
57 { 16, 0 }, { 17, 1 },
64 { 11, 0 }, { 13 , 1 },
66 { 4, 0 }, { 6, 3 }, { 12, 1 },
73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc()
76 case 0x10: in nvkm_gddr3_calc()
84 case 0x20: in nvkm_gddr3_calc()
85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr3_calc()
86 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_gddr3_calc()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dreset.c53 int err = 0; in mlx4_reset()
55 #define MLX4_RESET_BASE 0xf0000 in mlx4_reset()
56 #define MLX4_RESET_SIZE 0x400 in mlx4_reset()
57 #define MLX4_SEM_OFFSET 0x3fc in mlx4_reset()
58 #define MLX4_RESET_OFFSET 0x10 in mlx4_reset()
81 for (i = 0; i < 64; ++i) { in mlx4_reset()
92 reset = ioremap(pci_resource_start(dev->persist->pdev, 0) + in mlx4_reset()
128 &vendor) && vendor != 0xffff) in mlx4_reset()
134 if (vendor == 0xffff) { in mlx4_reset()
160 for (i = 0; i < 16; ++i) { in mlx4_reset()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]

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