Home
last modified time | relevance | path

Searched +full:0 +full:x3f8 (Results 1 – 25 of 59) sorted by relevance

123

/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/freebsd/stand/i386/btx/btx/
H A DMakefile8 BOOT_BTX_FLAGS=0x1
10 BOOT_BTX_FLAGS=0x0
17 BOOT_COMCONSOLE_PORT?= 0x3f8
19 B2SIOFMT?= 0x3
25 ORG= 0x9000
/freebsd/stand/man/
H A Dloader.efi.85 .\" Copyright (c) 2022 Mateusz Piotrowski <0mp@FreeBSD.org>
116 with an I/O address of 0x3f8.
149 .Dq io:0x3f8,br:115200
156 .It COM1 Ta 0x3f8 Ta Pa /dev/uart0
157 .It COM2 Ta 0x2f8 Ta Pa /dev/uart1
158 .It COM3 Ta 0x3e8 Ta Pa /dev/uart2
159 .It COM4 Ta 0x2e8 Ta Pa /dev/uart3
197 .It none Ta 0 Ta Video Ta Video
397 +Boot0001* FreeBSD ZPOOL HD(1,GPT,b5d0f86b-265d-1e1b-18aa-0ed55e1e73bd,0x28,0x96000)/File(\eEFI\eFR…
/freebsd/sys/amd64/conf/
H A DGENERIC.hints1 hint.atkbdc.0.at="isa"
2 hint.atkbdc.0.port="0x060"
3 hint.atkbd.0.at="atkbdc"
4 hint.atkbd.0.irq="1"
5 hint.psm.0.at="atkbdc"
6 hint.psm.0.irq="12"
7 hint.sc.0.at="isa"
8 hint.sc.0.flags="0x100"
9 hint.uart.0.at="acpi"
10 hint.uart.0.port="0x3F8"
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/freebsd/sys/i386/conf/
H A DGENERIC.hints1 hint.fdc.0.at="isa"
2 hint.fdc.0.port="0x3F0"
3 hint.fdc.0.irq="6"
4 hint.fdc.0.drq="2"
5 hint.fd.0.at="fdc0"
6 hint.fd.0.drive="0"
9 hint.ata.0.at="isa"
10 hint.ata.0.port="0x1F0"
11 hint.ata.0.irq="14"
13 hint.ata.1.port="0x170"
[all …]
/freebsd/stand/i386/gptboot/
H A DMakefile8 BOOT_COMCONSOLE_PORT?= 0x3f8
10 B2SIOFMT?= 0x3
12 REL1= 0x700
13 ORG1= 0x7c00
14 ORG2= 0x0
/freebsd/stand/i386/isoboot/
H A DMakefile9 BOOT_COMCONSOLE_PORT?= 0x3f8
11 B2SIOFMT?= 0x3
13 REL1= 0x700
14 ORG1= 0x7c00
15 ORG2= 0x0
43 echo "$$x bytes available"; test $$x -ge 0
/freebsd/stand/i386/libi386/
H A DMakefile39 BOOT_COMCONSOLE_PORT?= 0x3f8
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Dasinhf_3u5.c13 #define AbsMask (0x7fffffff)
14 #define SqrtFltMax (0x1.749e96p+10f)
15 #define Ln2 (0x1.62e4p-1f)
16 #define One (0x3f8)
17 #define ExpM12 (0x398)
25 asinhf(0x1.f0f74cp-1) got 0x1.b88de4p-1 want 0x1.b88de2p-1.
30 asinhf(0x1.00e358p+0) got 0x1.c4849ep-1 want 0x1.c484a2p-1.
36 asinhf(0x1.749e9ep+10) got 0x1.fffff8p+2 want 0x1.fffffep+2. */
46 if (unlikely (ia12 < ExpM12 || ia == 0x7f800000)) in asinhf()
49 if (unlikely (ia12 >= 0x7f8)) in asinhf()
[all …]
/freebsd/stand/i386/gptzfsboot/
H A DMakefile10 BOOT_COMCONSOLE_PORT?= 0x3f8
12 B2SIOFMT?= 0x3
14 REL1= 0x700
15 ORG1= 0x7c00
16 ORG2= 0x0
/freebsd/share/examples/etc/
H A Dmake.conf153 # parameters even when this is set to 0.
155 #BOOTWAIT=0
165 # COM1: = 0x3F8, COM2: = 0x2F8, COM3: = 0x3E8, COM4: = 0x2E8
167 #BOOT_COMCONSOLE_PORT= 0x3F8
/freebsd/stand/i386/boot2/
H A DMakefile5 # A value of 0x80 enables LBA support.
6 BOOT_BOOT1_FLAGS?= 0x80
8 BOOT_COMCONSOLE_PORT?= 0x3f8
10 B2SIOFMT?= 0x3
12 REL1= 0x700
13 ORG1= 0x7c00
14 ORG2= 0x2000
62 echo "$$x bytes available"; test $$x -ge 0
86 ${NM} -t d ${.ALLSRC} | awk '/([0-9])+ T xread/ \
/freebsd/stand/i386/zfsboot/
H A DMakefile8 BOOT_COMCONSOLE_PORT?= 0x3f8
10 B2SIOFMT?= 0x3
12 REL1= 0x700
13 ORG1= 0x7c00
14 ORG2= 0x2000
74 echo "$$x bytes available"; test $$x -ge 0
/freebsd/share/man/man5/
H A Ddevice.hints.5142 hint.uart.0.at="isa"
143 hint.uart.0.port="0x3F8"
144 hint.uart.0.flags="0x10"
145 hint.uart.0.irq="4"
150 hint.acpi.0.disabled="1"
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam57xx-sbc-am57x.dts25 DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
26 DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
38 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */
39 DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */
[all …]
/freebsd/sys/dev/sound/pci/
H A Dcs4281.h32 #define CS4281_PCI_ID 0x60051013
39 #define CS4281PCI_HISR 0x000
40 # define CS4281PCI_HISR_DMAI 0x00040000
41 # define CS4281PCI_HISR_DMA(x) (0x0100 << (x))
43 #define CS4281PCI_HICR 0x008
44 # define CS4281PCI_HICR_EOI 0x00000003
46 #define CS4281PCI_HIMR 0x00c
47 # define CS4281PCI_HIMR_DMAI 0x00040000
48 # define CS4281PCI_HIMR_DMA(x) (0x0100 << (x))
50 #define CS4281PCI_IIER 0x010
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dluks11 0 string LUKS\xba\xbe LUKS encrypted file,
21 >>0 use luks-v1
24 >>0 use luks-v2
28 0 name luks-v1
53 >208 ubelong =0x00AC71F3 \b; slot #0
56 >256 ubelong =0x00AC71F3 \b; slot #1
59 >304 ubelong =0x00AC71F3 \b; slot #2
62 >352 ubelong =0x00AC71F3 \b; slot #3
65 >400 ubelong =0x00AC71F3 \b; slot #4
68 >448 ubelong =0x00AC71F3 \b; slot #5
[all …]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A D8250.yaml231 reg = <0x80230000 0x100>;
240 reg = <0x49042000 0x400>;
255 reg = <0x1e787000 0x40>;
260 aspeed,lpc-io-reg = <0x3f8>;
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]

123