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/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/linux/arch/arm/mm/
H A Dproc-arm740.S48 mrc p15, 0, r0, c1, c0, 0
49 bic r0, r0, #0x3f000000 @ bank/f/lock/s
50 bic r0, r0, #0x0000000c @ w-buffer/cache
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mov ip, #0
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
65 bic ip, ip, #0x0000000c @ ............wc..
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
73 mov r0, #0
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi8 ranges = <0x7e000000 0x3f000000 0x1000000>,
9 <0x40000000 0x40000000 0x00001000>;
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 reg = <0x40000000 0x100>;
30 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
39 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
54 cpu-release-addr = <0x0 0x000000d8>;
55 d-cache-size = <0x8000>;
[all …]
H A Dbcm2836.dtsi9 ranges = <0x7e000000 0x3f000000 0x1000000>,
10 <0x40000000 0x40000000 0x00001000>;
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 reg = <0x40000000 0x100>;
31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
40 #size-cells = <0>;
51 v7_cpu0: cpu@0 {
54 reg = <0xf00>;
56 d-cache-size = <0x8000>;
59 i-cache-size = <0x8000>;
[all …]
/linux/drivers/cpufreq/
H A Dpowernow-k8.h43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
[all …]
/linux/drivers/firewire/
H A Dphy-packet-definitions.h10 #define PACKET_IDENTIFIER_MASK 0xc0000000
24 #define PHY_PACKET_PACKET_IDENTIFIER_PHY_CONFIG 0
26 #define PHY_CONFIG_ROOT_ID_MASK 0x3f000000
28 #define PHY_CONFIG_FORCE_ROOT_NODE_MASK 0x00800000
30 #define PHY_CONFIG_GAP_COUNT_OPTIMIZATION_MASK 0x00400000
32 #define PHY_CONFIG_GAP_COUNT_MASK 0x003f0000
81 #define SELF_ID_PHY_ID_MASK 0x3f000000
83 #define SELF_ID_EXTENDED_MASK 0x00800000
85 #define SELF_ID_MORE_PACKETS_MASK 0x00000001
86 #define SELF_ID_MORE_PACKETS_SHIFT 0
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_mips.h5 #define BCMA_MIPS_IPSFLAG 0x0F08
7 #define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
8 #define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
10 #define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
13 #define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
16 #define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
20 #define BCMA_MIPS_MIPS74K_CORECTL 0x0000
21 #define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
22 #define BCMA_MIPS_MIPS74K_BIST 0x000C
23 #define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
[all …]
/linux/arch/arm/nwfpe/
H A Dfpopcode.c19 { .high = 0x0000, .low = 0x0000000000000000ULL},/* extended 0.0 */
20 { .high = 0x3fff, .low = 0x8000000000000000ULL},/* extended 1.0 */
21 { .high = 0x4000, .low = 0x8000000000000000ULL},/* extended 2.0 */
22 { .high = 0x4000, .low = 0xc000000000000000ULL},/* extended 3.0 */
23 { .high = 0x4001, .low = 0x8000000000000000ULL},/* extended 4.0 */
24 { .high = 0x4001, .low = 0xa000000000000000ULL},/* extended 5.0 */
25 { .high = 0x3ffe, .low = 0x8000000000000000ULL},/* extended 0.5 */
26 { .high = 0x4002, .low = 0xa000000000000000ULL},/* extended 10.0 */
31 0x0000000000000000ULL, /* double 0.0 */
32 0x3ff0000000000000ULL, /* double 1.0 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_global_conf_masks.h24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
25 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
29 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
33 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10
37 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20
39 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40
41 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80
[all …]
/linux/arch/mips/math-emu/
H A Dsp_sqrt.c34 /* sqrt(0) = 0 */ in ieee754sp_sqrt()
60 if (m == 0) { /* subnormal x */ in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
73 s = 0; in ieee754sp_sqrt()
74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt()
75 r = 0x01000000; /* r = moving bit from right to left */ in ieee754sp_sqrt()
77 while (r != 0) { in ieee754sp_sqrt()
88 if (ix != 0) { in ieee754sp_sqrt()
99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
/linux/arch/arm/boot/dts/marvell/
H A Darmada-398-db.dts23 reg = <0x00000000 0x80000000>; /* 2 GB */
27 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
28 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
32 pinctrl-0 = <&i2c0_pins>;
39 pinctrl-0 = <&uart0_pins>;
45 pinctrl-0 = <&uart1_pins>;
62 pcie@1,0 {
66 pcie@2,0 {
70 pcie@3,0 {
79 pinctrl-0 = <&spi1_pins>;
[all …]
H A Darmada-390-db.dts24 reg = <0x00000000 0x80000000>; /* 2 GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
38 reg = <0x50>;
62 pcie@1,0 {
67 pcie@2,0 {
72 pcie@3,0 {
81 pinctrl-0 = <&spi1_pins>;
84 flash@0 {
89 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-375-db.dts24 memory@0 {
26 reg = <0x00000000 0x40000000>; /* 1 GB */
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
57 pinctrl-0 = <&spi0_pins>;
67 flash@0 {
[all …]
/linux/arch/m68k/fpsp040/
H A Dsatanh.S38 | atan(X) := sgn / (+0).
41 | 5. (|X| > 1) Generate an invalid operation by 0 * infinity.
71 andil #0x7FFFFFFF,%d0
72 cmpil #0x3FFF8000,%d0
82 fadds #0x3F800000,%fp1 | ...1-Y
85 andil #0x80000000,%d0
86 oril #0x3F000000,%d0 | ...SIGN(X)*HALF
99 fcmps #0x3F800000,%fp0
H A Dscosh.S63 T1: .long 0x40C62D38,0xD3D64634 | ... 16381 LOG2 LEAD
64 T2: .long 0x3D6F90AE,0xB1E75CC7 | ... 16381 LOG2 TRAIL
66 TWO16380: .long 0x7FFB0000,0x80000000,0x00000000,0x00000000
72 fmoves #0x3F800000,%fp0
75 fadds #0x00800000,%fp0
84 andil #0x7FFFFFFF,%d0
85 cmpil #0x400CB167,%d0
97 fmuls #0x3F000000,%fp0 | ...(1/2)EXP(|X|)
100 fmoves #0x3E800000,%fp1 | ...(1/4)
109 cmpil #0x400CB2B3,%d0
[all …]
H A Dssinh.S59 T1: .long 0x40C62D38,0xD3D64634 | ... 16381 LOG2 LEAD
60 T2: .long 0x3D6F90AE,0xB1E75CC7 | ... 16381 LOG2 TRAIL
81 andl #0x7FFFFFFF,%d0
82 cmpl #0x400CB167,%d0
94 fmovel #0,%fpcr
98 fadds #0x3F800000,%fp1 | ...1+Z
102 andl #0x80000000,%d0
103 orl #0x3F000000,%d0
113 cmpl #0x400CB2B3,%d0
117 movel #0,-(%sp)
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dravb.h39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
50 CCC = 0x0000,
51 DBAT = 0x0004,
52 DLR = 0x0008,
[all …]
/linux/include/net/
H A Dieee80211_radiotap.h29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/linux/drivers/media/rc/img-ir/
H A Dimg-ir.h20 #define IMG_IR_CONTROL 0x00
21 #define IMG_IR_STATUS 0x04
22 #define IMG_IR_DATA_LW 0x08
23 #define IMG_IR_DATA_UP 0x0c
24 #define IMG_IR_LEAD_SYMB_TIMING 0x10
25 #define IMG_IR_S00_SYMB_TIMING 0x14
26 #define IMG_IR_S01_SYMB_TIMING 0x18
27 #define IMG_IR_S10_SYMB_TIMING 0x1c
28 #define IMG_IR_S11_SYMB_TIMING 0x20
29 #define IMG_IR_FREE_SYMB_TIMING 0x24
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dreg_aic.h20 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
21 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
22 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
23 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
24 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
26 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
27 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
28 #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
30 #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
31 #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dga100.c33 int i, n, size = nvkm_rd32(device, 0x0224fc) >> 20; in ga100_top_parse()
35 for (i = 0, n = 0; i < size; i++) { in ga100_top_parse()
39 type = ~0; in ga100_top_parse()
40 inst = 0; in ga100_top_parse()
43 data = nvkm_rd32(device, 0x022800 + (i * 0x04)); in ga100_top_parse()
45 if (!data && n == 0) in ga100_top_parse()
49 case 0: in ga100_top_parse()
50 type = (data & 0x3f000000) >> 24; in ga100_top_parse()
51 inst = (data & 0x000f0000) >> 16; in ga100_top_parse()
52 info->fault = (data & 0x0000007f); in ga100_top_parse()
[all …]
/linux/arch/mips/loongson2ef/common/cs5536/
H A Dcs5536_ehci.c17 u32 hi = 0, lo = value; in pci_ehci_write_reg()
37 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_ehci_write_reg()
47 } else if ((value & 0x01) == 0x00) { in pci_ehci_write_reg()
52 value &= 0xfffffff0; in pci_ehci_write_reg()
53 hi = 0x40000000 | ((value & 0xff000000) >> 24); in pci_ehci_write_reg()
54 lo = 0x000fffff | ((value & 0x00fff000) << 8); in pci_ehci_write_reg()
60 hi &= 0x003f0000; in pci_ehci_write_reg()
61 hi |= (value & 0x3f) << 16; in pci_ehci_write_reg()
66 hi &= ~0x00003f00; in pci_ehci_write_reg()
67 hi |= value & 0x00003f00; in pci_ehci_write_reg()
[all …]

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