Searched +full:0 +full:x3e200 (Results 1 – 8 of 8) sorted by relevance
54 * at the time it indicated completion is stored there. Returns 0 if the66 return 0; in t4_wait_op_done_val()68 if (--attempts == 0) in t4_wait_op_done_val()167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()169 * ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()247 log->cursor = 0; in t4_record_mbox()249 for (i = 0; i < size / 8; i++) in t4_record_mbox()252 entry->cmd[i++] = 0; in t4_record_mbox()277 * The return value is 0 on success or a negative errno on failure. A[all …]
29 // base address: 0x498030 …SDMA0_DEC_START 0x000031 …e regSDMA0_DEC_START_BASE_IDX 032 …SDMA0_F32_MISC_CNTL 0x000b33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 034 …SDMA0_UCODE_VERSION 0x000d35 …e regSDMA0_UCODE_VERSION_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 038 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010[all …]
24 …SQ_DEBUG_STS_GLOBAL 0x10A925 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 026 …SQ_DEBUG_STS_GLOBAL2 0x10B027 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 030 // base address: 0x498031 …SDMA0_DEC_START 0x000032 …ne mmSDMA0_DEC_START_BASE_IDX 033 …SDMA0_PG_CNTL 0x001634 …ne mmSDMA0_PG_CNTL_BASE_IDX 035 …SDMA0_PG_CTX_LO 0x0017[all …]
29 // base address: 0x498030 …SDMA0_DEC_START 0x000031 …e regSDMA0_DEC_START_BASE_IDX 032 …SDMA0_F32_MISC_CNTL 0x000b33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 034 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_HI 0x001037 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 038 …SDMA0_POWER_CNTL 0x001a[all …]
29 // base address: 0x498030 …SDMA0_DEC_START 0x000031 …e regSDMA0_DEC_START_BASE_IDX 032 …SDMA0_MCU_MISC_CNTL 0x000133 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 034 …SDMA0_UCODE_REV 0x000335 …e regSDMA0_UCODE_REV_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000537 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 038 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006[all …]
25 …SQ_DEBUG_STS_GLOBAL 0x10A926 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 027 …SQ_DEBUG_STS_GLOBAL2 0x10B028 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 029 …SQ_DEBUG 0x10B130 …ne mmSQ_DEBUG_BASE_IDX 033 // base address: 0x498034 …SDMA0_DEC_START 0x000035 …ne mmSDMA0_DEC_START_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f[all …]
71 #define BAR_0 0105 #define RESET_KIND_SHUTDOWN 0109 #define TG3_DEF_RX_MODE 0110 #define TG3_DEF_TX_MODE 0195 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)201 #if (NET_IP_ALIGN != 0)234 module_param(tg3_debug, int, 0);237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */[all …]