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/linux/arch/powerpc/include/asm/
H A Ddisassemble.h21 return (inst >> 1) & 0x3ff; in get_xop()
26 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_sprn()
31 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_dcrn()
36 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_tmrn()
41 return (inst >> 21) & 0x1f; in get_rt()
46 return (inst >> 21) & 0x1f; in get_rs()
51 return (inst >> 16) & 0x1f; in get_ra()
56 return (inst >> 11) & 0x1f; in get_rb()
61 return inst & 0x1; in get_rc()
66 return (inst >> 11) & 0x1f; in get_ws()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
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H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
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/linux/arch/sparc/include/asm/
H A Dintr_queue.h7 #define INTRQ_CPU_MONDO_HEAD 0x3c0 /* CPU mondo head */
8 #define INTRQ_CPU_MONDO_TAIL 0x3c8 /* CPU mondo tail */
9 #define INTRQ_DEVICE_MONDO_HEAD 0x3d0 /* Device mondo head */
10 #define INTRQ_DEVICE_MONDO_TAIL 0x3d8 /* Device mondo tail */
11 #define INTRQ_RESUM_MONDO_HEAD 0x3e0 /* Resumable error mondo head */
12 #define INTRQ_RESUM_MONDO_TAIL 0x3e8 /* Resumable error mondo tail */
13 #define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
14 #define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_mme_ctrl_lo_masks.h24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0
25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F
27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20
29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40
31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180
33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00
35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000
37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000
39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000
41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000
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/linux/arch/alpha/include/asm/
H A Dvga.h59 (((a) >= 0x3b0) && ((a) < 0x3e0) && \
60 ((a) != 0x3b3) && ((a) != 0x3d3))
63 (((a) >= 0xa0000) && ((a) <= 0xc0000))
68 } while(0)
73 } while(0)
76 # define pci_vga_hose 0
77 # define __is_port_vga(a) 0
78 # define __is_mem_vga(a) 0
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
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H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
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H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
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H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
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/linux/tools/testing/selftests/kvm/include/x86_64/
H A Dapic.h16 #define APIC_DEFAULT_GPA 0xfee00000ULL
19 #define MSR_IA32_APICBASE 0x0000001b
23 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
26 #define APIC_BASE_MSR 0x800
28 #define APIC_ID 0x20
29 #define APIC_LVR 0x30
30 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)
31 #define APIC_TASKPRI 0x80
32 #define APIC_PROCPRI 0xA0
33 #define APIC_EOI 0xB0
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H A Dsvm.h80 #define HV_SVM_EXITCODE_ENL 0xf0000000
119 u64 avic_backing_page; /* Offset 0xe0 */
120 u8 reserved_6[8]; /* Offset 0xe8 */
121 u64 avic_logical_id; /* Offset 0xf0 */
122 u64 avic_physical_id; /* Offset 0xf8 */
127 * Offset 0x3e0, 32 bytes reserved
137 #define TLB_CONTROL_DO_NOTHING 0
142 #define V_TPR_MASK 0x0f
151 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
165 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dcache.json46 "EventCode": "0x49",
52 "EventCode": "0x59",
58 "EventCode": "0x200",
64 "EventCode": "0x202",
70 "EventCode": "0x208",
76 "EventCode": "0x209",
82 "EventCode": "0x300",
88 "EventCode": "0x302",
94 "EventCode": "0x308",
100 "EventCode": "0x309",
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/linux/include/linux/
H A Dtc.h29 #define TC_OLDCARD 0x3c0000
30 #define TC_NEWCARD 0x000000
32 #define TC_ROM_WIDTH 0x3e0
33 #define TC_ROM_STRIDE 0x3e4
34 #define TC_ROM_SIZE 0x3e8
35 #define TC_SLOT_SIZE 0x3ec
36 #define TC_PATTERN0 0x3f0
37 #define TC_PATTERN1 0x3f4
38 #define TC_PATTERN2 0x3f8
39 #define TC_PATTERN3 0x3fc
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/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
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/linux/sound/isa/msnd/
H A Dmsnd_pinnacle.c95 snd_msnd_DAPQ(chip, 0); in snd_msnd_eval_dsp_msg()
100 chip->playDMAPos = 0; in snd_msnd_eval_dsp_msg()
111 chip->captureDMAPos = 0; in snd_msnd_eval_dsp_msg()
139 ": DSP message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
151 dev_dbg(chip->card->dev, LOGNAME ": HIMT message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
175 head = 0; in snd_msnd_interrupt()
198 while (timeout-- > 0) { in snd_msnd_reset_dsp()
200 return 0; in snd_msnd_reset_dsp()
223 if (snd_msnd_reset_dsp(chip, &info) < 0) { in snd_msnd_probe()
232 "I/O 0 in snd_msnd_probe()
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/linux/drivers/media/pci/mgb4/
H A Dmgb4_sysfs_in.c39 i2c_reg = MGB4_IS_GMSL(mgbdev) ? 0x1CE : 0x49; in oldi_lane_width_show()
40 i2c_mask = MGB4_IS_GMSL(mgbdev) ? 0x0E : 0x03; in oldi_lane_width_show()
41 i2c_single_val = MGB4_IS_GMSL(mgbdev) ? 0x00 : 0x02; in oldi_lane_width_show()
42 i2c_dual_val = MGB4_IS_GMSL(mgbdev) ? 0x0E : 0x00; in oldi_lane_width_show()
47 if (ret < 0) in oldi_lane_width_show()
58 return sprintf(buf, "%s\n", config & (1U << 9) ? "1" : "0"); in oldi_lane_width_show()
83 case 0: /* single */ in oldi_lane_width_store()
84 fpga_data = 0; in oldi_lane_width_store()
85 i2c_data = MGB4_IS_GMSL(mgbdev) ? 0x00 : 0x02; in oldi_lane_width_store()
89 i2c_data = MGB4_IS_GMSL(mgbdev) ? 0x0E : 0x00; in oldi_lane_width_store()
[all …]
/linux/drivers/media/pci/tw68/
H A Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
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/linux/arch/x86/include/asm/
H A Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_DELIVERY_MODE_FIXED 0
30 #define APIC_ID 0x20
32 #define APIC_LVR 0x30
33 #define APIC_LVR_MASK 0xFF00FF
35 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
38 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
42 #define APIC_XAPIC(x) ((x) >= 0x14)
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/linux/drivers/usb/host/
H A Dxhci-caps.h4 /* bits 7:0 - how long is the Capabilities register */
7 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
10 /* bits 0:7, Max Device Slots */
11 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
12 #define HCS_SLOTS_MASK 0xff
14 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
15 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
16 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
19 /* bits 0:3, frames or uframes that SW needs to queue transactions
21 #define HCS_IST(p) (((p) >> 0) & 0xf)
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra30-pinmux.yaml147 reg = <0x70000868 0x0d0>, /* Pad control registers */
148 <0x70003000 0x3e0>; /* Mux registers */
155 nvidia,pull = <0>;
156 nvidia,tristate = <0>;
170 nvidia,tristate = <0>;
/linux/arch/loongarch/include/asm/
H A Dloongson.h20 #define LOONGSON_LIO_BASE 0x18000000
21 #define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
24 #define LOONGSON_BOOT_BASE 0x1c000000
25 #define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
28 #define LOONGSON_REG_BASE 0x1fe00000
29 #define LOONGSON_REG_SIZE 0x00100000 /* 1M */
34 #define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
35 #define LOONGSON_GPIOIE LOONGSON_REG(0x120)
36 #define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
46 " st.w %[v], %[hw], 0 \n" in xconf_writel()
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h12 /* [31: 4] Reserved. Default 0.
14 * 1=Assert SW reset of timing feature. 0=Release reset.
16 * 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset.
18 * 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset.
19 * [0] RW dwc_rst_n: Default 1.
20 * 1=Assert SW reset on IP core. 0=Release reset.
22 #define MIPI_DSI_TOP_SW_RESET 0x3c0
24 #define MIPI_DSI_TOP_SW_RESET_DWC BIT(0)
29 /* [31: 5] Reserved. Default 0.
30 * [4] RW manual_edpihalt: Default 0.
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Di2c.c31 u16 i2c = 0x0000; in dcb_i2c_table()
34 if (*ver >= 0x15) in dcb_i2c_table()
36 if (*ver >= 0x30) in dcb_i2c_table()
40 if (i2c && *ver >= 0x42) { in dcb_i2c_table()
42 return 0x0000; in dcb_i2c_table()
45 if (i2c && *ver >= 0x30) { in dcb_i2c_table()
46 *ver = nvbios_rd08(bios, i2c + 0); in dcb_i2c_table()
52 *hdr = 0; in dcb_i2c_table()
67 return 0x0000; in dcb_i2c_entry()
77 if (ver >= 0x41) { in dcb_i2c_parse()
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/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-evm-common.dtsi90 #size-cells = <0>;
123 <&dra7_pmx_core 0x3e0>;
138 flash@0 {
141 reg = <0>;
152 partition@0 {
154 reg = <0x00000000 0x00010000>;
158 reg = <0x00010000 0x00010000>;
162 reg = <0x00020000 0x00010000>;
166 reg = <0x00030000 0x00010000>;
170 reg = <0x00040000 0x00100000>;
[all …]

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