Searched +full:0 +full:x3c00000 (Results 1 – 20 of 20) sorted by relevance
11 partition@0 {13 reg = <0x0 0x10000>;19 reg = <0x10000 0xfff0000>;24 reg = <0xf0000 0x10000>;29 reg = <0x100000 0x80000>;34 reg = <0x180000 0x200000>;39 reg = <0x380000 0x10000>;44 reg = <0x390000 0x10000>;49 reg = <0x400000 0x3c00000>;54 reg = <0x4010000 0x20000>;[all …]
20 reg = <0x20000000 0x4000000>;28 main_clock: clock@0 {43 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;48 reg = <0x3 0x0 0x800000>;62 kernel@0 {64 reg = <0x0 0x400000>;69 reg = <0x400000 0x3C00000>;74 reg = <0x4000000 0x2000000>;79 reg = <0x6000000 0x2000000>;107 pinctrl-0 = <&pinctrl_ssc0_tx>;[all …]
22 reg = <0x70000000 0x4000000>;42 timer@0 {44 reg = <0>, <1>;54 pinctrl-0 =70 reg = <0x30>;72 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;98 pinctrl-0 = <104 slot@0 {105 reg = <0>;112 pinctrl-0 = <[all …]
136 reg = <0x3300000 0x30000>,137 <0x32a9000 0x1000>;154 reg = <0x3c00000 0x28>;168 reg = <0x3900000 0x50000>;183 reg = <0x3380000 0x30000>;
2 #define AUD_COMM_EXEC__A 0x10000003 #define AUD_COMM_EXEC_STOP 0x04 #define FEC_COMM_EXEC__A 0x1C000005 #define FEC_COMM_EXEC_STOP 0x06 #define FEC_COMM_EXEC_ACTIVE 0x17 #define FEC_DI_COMM_EXEC__A 0x1C200008 #define FEC_DI_COMM_EXEC_STOP 0x09 #define FEC_DI_INPUT_CTL__A 0x1C2001610 #define FEC_RS_COMM_EXEC__A 0x1C3000011 #define FEC_RS_COMM_EXEC_STOP 0x0[all …]
27 #define IH_VMID_0_LUT__PASID_MASK 0xffff28 #define IH_VMID_0_LUT__PASID__SHIFT 0x029 #define IH_VMID_1_LUT__PASID_MASK 0xffff30 #define IH_VMID_1_LUT__PASID__SHIFT 0x031 #define IH_VMID_2_LUT__PASID_MASK 0xffff32 #define IH_VMID_2_LUT__PASID__SHIFT 0x033 #define IH_VMID_3_LUT__PASID_MASK 0xffff34 #define IH_VMID_3_LUT__PASID__SHIFT 0x035 #define IH_VMID_4_LUT__PASID_MASK 0xffff36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0[all …]
26 qcom,msm-id = <339 0x20000>; /* SM8150 v2 */27 qcom,board-id = <8 0>;36 reg = <0 0x9c000000 0 0x2300000>;55 pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>;91 pinctrl-0 = <&main_cam_pwr_en>;101 pinctrl-0 = <&sub_cam_pwr_en>;111 pinctrl-0 = <&chat_cam_pwr_en>;121 pinctrl-0 = <&supwc_pwr_en>;131 pinctrl-0 = <&main_cam_pwr_vmdr_en>;141 pinctrl-0 = <&rgbc_ir_pwr_en>;[all …]
34 #define XSDFEC_CODE_WR_PROTECT_ADDR (0x4)37 #define XSDFEC_ACTIVE_ADDR (0x8)38 #define XSDFEC_IS_ACTIVITY_SET (0x1)41 #define XSDFEC_AXIS_WIDTH_ADDR (0xC)45 #define XSDFEC_AXIS_DIN_WIDTH_LSB (0)48 #define XSDFEC_AXIS_ENABLE_ADDR (0x10)49 #define XSDFEC_AXIS_OUT_ENABLE_MASK (0x38)50 #define XSDFEC_AXIS_IN_ENABLE_MASK (0x7)55 #define XSDFEC_FEC_CODE_ADDR (0x14)58 #define XSDFEC_ORDER_ADDR (0x18)[all …]
27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x029 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x40030 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x033 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x100034 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc35 #define THM_TCON_HTC__HTC_EN_MASK 0x136 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0[all …]
27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x029 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x031 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x033 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x035 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x836 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3[all …]
27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x029 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x031 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x033 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x035 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x136 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0[all …]
27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x128 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x029 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x130 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x031 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x033 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x300000034 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x1835 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x1000000036 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c[all …]
27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff28 #define MM_INDEX__MM_OFFSET__SHIFT 0x029 #define MM_INDEX__MM_APER_MASK 0x8000000030 #define MM_INDEX__MM_APER__SHIFT 0x1f31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x033 #define MM_DATA__MM_DATA_MASK 0xffffffff34 #define MM_DATA__MM_DATA__SHIFT 0x035 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x236 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1[all …]
27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff28 #define MM_INDEX__MM_OFFSET__SHIFT 0x029 #define MM_INDEX__MM_APER_MASK 0x8000000030 #define MM_INDEX__MM_APER__SHIFT 0x1f31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x033 #define MM_DATA__MM_DATA_MASK 0xffffffff34 #define MM_DATA__MM_DATA__SHIFT 0x035 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x236 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1[all …]