Home
last modified time | relevance | path

Searched +full:0 +full:x3a00 (Results 1 – 25 of 27) sorted by relevance

12

/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux/arch/powerpc/boot/dts/
H A Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021.dtsi23 #clock-cells = <0>;
33 ranges = <0 0x9c000000 0x400000>;
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
47 reg = <0x780 0x80>, <0xa80 0x80>;
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
62 reg = <0x14 0x3>;
65 reg = <0x18 0x2>;
68 reg = <0x34 0x6>;
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/include/soc/fsl/qe/
H A Dimmap_qe.h26 u8 res0[0x04];
28 u8 res1[0x70];
44 u8 res0[0x4];
47 u8 res1[0x4];
49 u8 res2[0x20];
51 u8 res3[0x1C];
59 u8 res0[0xA];
61 u8 res1[0x2];
66 u8 res2[0x8];
70 u8 res3[0x2];
[all …]
/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/linux/include/linux/qed/
H A Dcommon_hsi.h16 #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
23 } while (0)
47 #define ISCSI_CDU_TASK_SEG_TYPE 0
48 #define FCOE_CDU_TASK_SEG_TYPE 0
59 #define YSTORM_QZONE_SIZE 0
60 #define PSTORM_QZONE_SIZE 0
97 #define FW_ENGINEERING_VERSION 0
158 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
161 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
163 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz_common.c38 #define MIB_COUNTER_NUM 0x20
41 { 0x00, "rx" },
42 { 0x01, "rx_hi" },
43 { 0x02, "rx_undersize" },
44 { 0x03, "rx_fragments" },
45 { 0x04, "rx_oversize" },
46 { 0x05, "rx_jabbers" },
47 { 0x06, "rx_symbol_err" },
48 { 0x07, "rx_crc_err" },
49 { 0x08, "rx_align_err" },
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dpci.h10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA03 0x03
17 #define RAC_ANA09 0x09
19 #define RAC_ANA0A 0x0A
21 #define RAC_ANA0B 0x0B
23 #define RAC_ANA0C 0x0C
25 #define RAC_ANA0D 0x0D
28 #define RAC_ANA10 0x10
30 #define ADDR_SEL_VAL 0x3C
[all …]
/linux/drivers/net/wireless/ath/ar5523/
H A Dar5523.c56 if (dlen < 0) { in ar5523_read_reply()
61 ar5523_dbg(ar, "Code = %d len = %d\n", be32_to_cpu(hdr->code) & 0xff, in ar5523_read_reply()
66 olen = be32_to_cpu(rp[0]); in ar5523_read_reply()
68 if (olen == 0) { in ar5523_read_reply()
69 /* convention is 0 =>'s one word */ in ar5523_read_reply()
73 olen = 0; in ar5523_read_reply()
79 cmd->olen = 0; in ar5523_read_reply()
84 cmd->res = 0; in ar5523_read_reply()
112 be32_to_cpu(hdr->code) & 0xff, hdr->priv); in ar5523_cmd_rx_cb()
117 switch (code & 0xff) { in ar5523_cmd_rx_cb()
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/media/i2c/
H A Dov5640.c43 #define OV5640_DEFAULT_SLAVE_ID 0x3c
47 #define OV5640_REG_SYS_RESET02 0x3002
48 #define OV5640_REG_SYS_CLOCK_ENABLE02 0x3006
49 #define OV5640_REG_SYS_CTRL0 0x3008
50 #define OV5640_REG_SYS_CTRL0_SW_PWDN 0x42
51 #define OV5640_REG_SYS_CTRL0_SW_PWUP 0x02
52 #define OV5640_REG_SYS_CTRL0_SW_RST 0x82
53 #define OV5640_REG_CHIP_ID 0x300a
54 #define OV5640_REG_IO_MIPI_CTRL00 0x300e
55 #define OV5640_REG_PAD_OUTPUT_ENABLE01 0x3017
[all …]
H A Dov64a40.c28 #define OV64A40_PIXEL_ARRAY_TOP 0
29 #define OV64A40_PIXEL_ARRAY_LEFT 0
38 #define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301)
39 #define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303)
40 #define OV64A40_PLL1_MULTIPLIER CCI_REG16(0x0304)
41 #define OV64A40_PLL1_M_DIV CCI_REG8(0x0307)
42 #define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320)
43 #define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323)
44 #define OV64A40_PLL2_MULTIPLIER CCI_REG16(0x0324)
45 #define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326)
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c.c21 #define IQK_DONE_8822C 0xaa
57 efuse->country_code[0] = map->country_code[0]; in rtw8822c_read_efuse()
60 efuse->regd = map->rf_board_option & 0x7; in rtw8822c_read_efuse()
65 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; in rtw8822c_read_efuse()
67 for (i = 0; i < 4; i++) in rtw8822c_read_efuse()
85 return 0; in rtw8822c_read_efuse()
115 u32 rf_addr[DACK_RF_8822C] = {0x8f}; in rtw8822c_dac_backup_reg()
116 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, in rtw8822c_dac_backup_reg()
117 0x1c3c, 0x1c24, 0x1d70, 0x9b4, in rtw8822c_dac_backup_reg()
118 0x1a00, 0x1a14, 0x1d58, 0x1c38, in rtw8822c_dac_backup_reg()
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie.c74 [QPHY_SW_RESET] = 0x00,
75 [QPHY_START_CTRL] = 0x08,
76 [QPHY_PCS_STATUS] = 0x2ac,
77 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]

12