Searched +full:0 +full:x3e800 (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | sa8540p-ride.dts | 34 regulators-0 {
162 pinctrl-0 = <ðernet0_default>;
169 #size-cells = <0>;
173 compatible = "ethernet-phy-id0141.0dd4";
174 reg = <0x8>;
188 /* Set MODE[2:0] to RGMII_SGMII */
189 <0x12 0x14 0xfff8 0x4>,
190 /* Soft reset required after changing MODE[2:0] */
191 <0x12 0x14 0x7fff 0x8000>;
201 snps,map-to-dma-channel = <0x0>;
[all …]
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_12_0_0_offset.h | 29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
|
| H A D | gc_11_0_3_offset.h | 29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
|
| /linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_dump.h | 22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
|