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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imxrt1170.yaml71 reg = <0x400e8000 0x4000>;
74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/freebsd/usr.sbin/bhyve/amd64/
H A Dvga.h32 #define VGA_IOPORT_START 0x3c0
33 #define VGA_IOPORT_END 0x3df
36 #define GEN_INPUT_STS0_PORT 0x3c2
37 #define GEN_FEATURE_CTRL_PORT 0x3ca
38 #define GEN_MISC_OUTPUT_PORT 0x3cc
39 #define GEN_INPUT_STS1_MONO_PORT 0x3ba
40 #define GEN_INPUT_STS1_COLOR_PORT 0x3da
41 #define GEN_IS1_VR 0x08 /* Vertical retrace */
42 #define GEN_IS1_DE 0x01 /* Display enable not */
45 #define ATC_IDX_PORT 0x3c0
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Dpci.h17 #define RTK_PCI_CTRL 0x300
20 #define REG_DBI_WDATA_V1 0x03E8
21 #define REG_DBI_RDATA_V1 0x03EC
22 #define REG_DBI_FLAG_V1 0x03F0
28 #define REG_MDIO_V1 0x03F4
29 #define REG_PCIE_MIX_CFG 0x03F8
30 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
33 #define RTW_PCI_MDIO_PG_OFFS_G1 0
37 #define RTK_PCIE_LINK_CFG 0x0719
40 #define BIT_CLKREQ_N_PAD BIT(0)
[all …]
/freebsd/sys/arm64/broadcom/genet/
H A Dif_genetreg.h38 #define GENET_SYS_REV_CTRL 0x000
41 #define REV_MAJOR 0xf000000
44 #define REV_MINOR 0xf0000
46 #define REV_PHY 0xffff
47 #define GENET_SYS_PORT_CTRL 0x004
49 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008
51 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c
52 #define GENET_EXT_RGMII_OOB_CTRL 0x08c
57 #define GENET_INTRL2_CPU_STAT 0x200
58 #define GENET_INTRL2_CPU_CLEAR 0x208
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_car.h38 #define RST_DEVICES_L 0x004
39 #define RST_DEVICES_H 0x008
40 #define RST_DEVICES_U 0x00C
41 #define CLK_OUT_ENB_L 0x010
42 #define CLK_OUT_ENB_H 0x014
43 #define CLK_OUT_ENB_U 0x018
44 #define CCLK_BURST_POLICY 0x020
45 #define SUPER_CCLK_DIVIDER 0x024
46 #define SCLK_BURST_POLICY 0x028
47 #define SUPER_SCLK_DIVIDER 0x02c
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_car.h39 #define RST_SOURCE 0x000
40 #define RST_DEVICES_L 0x004
41 #define RST_DEVICES_H 0x008
42 #define RST_DEVICES_U 0x00C
43 #define CLK_OUT_ENB_L 0x010
44 #define CLK_OUT_ENB_H 0x014
45 #define CLK_OUT_ENB_U 0x018
46 #define SUPER_CCLK_DIVIDER 0x024
47 #define SCLK_BURST_POLICY 0x028
48 #define SUPER_SCLK_DIVIDER 0x02c
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
H A Dosprey_reg_map.h86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/tools/tools/cxgbtool/
H A Dreg_defs.c7 { "SG_CONTROL", 0x0, 0 },
8 { "CmdQ0_Enable", 0, 1 },
24 { "SG_DOORBELL", 0x4, 0 },
25 { "CmdQ0_Enable", 0, 1 },
29 { "SG_CMD0BASELWR", 0x8, 0 },
30 { "SG_CMD0BASEUPR", 0xc, 0 },
31 { "SG_CMD1BASELWR", 0x10, 0 },
32 { "SG_CMD1BASEUPR", 0x14, 0 },
33 { "SG_FL0BASELWR", 0x18, 0 },
34 { "SG_FL0BASEUPR", 0x1c, 0 },
[all …]
/freebsd/sys/riscv/include/
H A Dencoding.h8 #define MATCH_BEQ 0x63
9 #define MASK_BEQ 0x707f
10 #define MATCH_BNE 0x1063
11 #define MASK_BNE 0x707f
12 #define MATCH_BLT 0x4063
13 #define MASK_BLT 0x707f
14 #define MATCH_BGE 0x5063
15 #define MASK_BGE 0x707f
16 #define MATCH_BLTU 0x6063
17 #define MASK_BLTU 0x707f
[all …]
/freebsd/sys/powerpc/powerpc/
H A Ddb_disasm.c17 Op_A = 0x00000001,
18 Op_B = 0x00000002,
19 Op_BI = 0x00000004,
20 Op_BO = 0x00000008,
22 Op_CRM = 0x00000010,
23 Op_D = 0x00000020,
24 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */
25 Op_S = 0x00000040, /* S-field is swapped with A-field */
27 Op_dA = 0x00000080,
28 Op_LK = 0x00000100,
[all …]

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