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/linux/Documentation/devicetree/bindings/sound/
H A Dalc5623.txt11 Register. If absent or has the value of 0, the
15 Control Register. If absent or has value 0, the
22 reg = <0x1a>;
23 add-ctrl = <0x3700>;
24 jack-det-ctrl = <0x4810>;
/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt715.h30 #define RT715_AUDIO_FUNCTION_GROUP 0x01
31 #define RT715_MIC_ADC 0x07
32 #define RT715_LINE_ADC 0x08
33 #define RT715_MIX_ADC 0x09
34 #define RT715_DMIC1 0x12
35 #define RT715_DMIC2 0x13
36 #define RT715_MIC1 0x18
37 #define RT715_MIC2 0x19
38 #define RT715_LINE1 0x1a
39 #define RT715_LINE2 0x1b
[all …]
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
[all …]
H A Drt5663.c31 #define RT5663_DEVICE_ID_2 0x6451
32 #define RT5663_DEVICE_ID_1 0x6406
81 { 0x002a, 0x8020 },
82 { 0x0086, 0x0028 },
83 { 0x0100, 0xa020 },
84 { 0x0117, 0x0f28 },
85 { 0x02fb, 0x8089 },
89 { 0x0000, 0x0000 },
90 { 0x0001, 0xc8c8 },
91 { 0x0002, 0x8080 },
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-t5325.dts23 reg = <0x00000000 0x20000000>;
33 pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
76 flash@0 {
81 reg = <0>;
82 mode = <0>;
84 partition@0 {
85 reg = <0x0 0x80000>;
90 reg = <0x80000 0x40000>;
95 reg = <0xc0000 0x10000>;
100 reg = <0xd0000 0x10000>;
[all …]
/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
H A Doss_3_0_1_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
H A Doss_3_0_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/drivers/media/i2c/
H A Dov5695.c30 #define CHIP_ID 0x005695
31 #define OV5695_REG_CHIP_ID 0x300a
33 #define OV5695_REG_CTRL_MODE 0x0100
34 #define OV5695_MODE_SW_STANDBY 0x0
35 #define OV5695_MODE_STREAMING BIT(0)
37 #define OV5695_REG_EXPOSURE 0x3500
40 #define OV5695_VTS_MAX 0x7fff
42 #define OV5695_REG_ANALOG_GAIN 0x3509
43 #define ANALOG_GAIN_MIN 0x10
44 #define ANALOG_GAIN_MAX 0xf8
[all …]
H A Dov8865.c28 #define OV8865_SW_STANDBY_REG 0x100
29 #define OV8865_SW_STANDBY_STREAM_ON BIT(0)
31 #define OV8865_SW_RESET_REG 0x103
32 #define OV8865_SW_RESET_RESET BIT(0)
34 #define OV8865_PLL_CTRL0_REG 0x300
35 #define OV8865_PLL_CTRL0_PRE_DIV(v) ((v) & GENMASK(2, 0))
36 #define OV8865_PLL_CTRL1_REG 0x301
38 #define OV8865_PLL_CTRL2_REG 0x302
39 #define OV8865_PLL_CTRL2_MUL_L(v) ((v) & GENMASK(7, 0))
40 #define OV8865_PLL_CTRL3_REG 0x303
[all …]
H A Dov4689.c23 #define OV4689_REG_CTRL_MODE CCI_REG8(0x0100)
24 #define OV4689_MODE_SW_STANDBY 0x0
25 #define OV4689_MODE_STREAMING BIT(0)
27 #define OV4689_REG_CHIP_ID CCI_REG16(0x300a)
28 #define CHIP_ID 0x004688
30 #define OV4689_REG_EXPOSURE CCI_REG24(0x3500)
34 #define OV4689_REG_GAIN CCI_REG16(0x3508)
36 #define OV4689_GAIN_DEFAULT 0x80
38 #define OV4689_REG_DIG_GAIN CCI_REG16(0x352a)
40 #define OV4689_DIG_GAIN_MAX 0x7fff
[all …]
H A Dov5693.c32 #define OV5693_SW_RESET_REG CCI_REG8(0x0103)
33 #define OV5693_SW_STREAM_REG CCI_REG8(0x0100)
34 #define OV5693_START_STREAMING 0x01
35 #define OV5693_STOP_STREAMING 0x00
36 #define OV5693_SW_RESET 0x01
38 #define OV5693_REG_CHIP_ID CCI_REG16(0x300a)
39 /* Yes, this is right. The datasheet for the OV5693 gives its ID as 0x5690 */
40 #define OV5693_CHIP_ID 0x5690
43 #define OV5693_EXPOSURE_CTRL_REG CCI_REG24(0x3500)
50 #define OV5693_GAIN_CTRL_REG CCI_REG16(0x350a)
[all …]
H A Dov5648.c30 #define OV5648_SW_STANDBY_REG 0x100
31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0)
33 #define OV5648_SW_RESET_REG 0x103
34 #define OV5648_SW_RESET_RESET BIT(0)
36 #define OV5648_PAD_OEN0_REG 0x3000
37 #define OV5648_PAD_OEN1_REG 0x3001
38 #define OV5648_PAD_OEN2_REG 0x3002
39 #define OV5648_PAD_OUT0_REG 0x3008
40 #define OV5648_PAD_OUT1_REG 0x3009
42 #define OV5648_CHIP_ID_H_REG 0x300a
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc-ctrl.c41 #define GET_STATUS_B00 0x0B00
42 #define SENSOR_TYPE_FORMATTER1 0x0C00
43 #define GET_STATUS_3000 0x3000
44 #define READ_RAW_Y_MEAN_FORMATTER 0x3100
45 #define SET_POWER_SAVE_MODE_FORMATTER 0x3200
46 #define MIRROR_IMAGE_FORMATTER 0x3300
47 #define LED_FORMATTER 0x3400
48 #define LOWLIGHT 0x3500
49 #define GET_STATUS_3600 0x3600
50 #define SENSOR_TYPE_FORMATTER2 0x3700
[all …]
/linux/drivers/media/usb/gspca/
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm816x.dtsi27 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
61 reg = <0x44000000 0x10000>;
69 reg = <0x48180000 0x4000>;
72 ranges = <0 0x48180000 0x4000>;
76 #size-cells = <0>;
85 reg = <0x48140000 0x21000>;
89 ranges = <0 0x48140000 0x21000>;
93 reg = <0x800 0x50a>;
[all …]
/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/scsi/mpt3sas/
H A Dmpt3sas_base.h91 #define MPT2SAS_BUILD_VERSION 0
96 #define MPT3SAS_COREDUMP_LOOP_DONE (0xFF)
99 #define MPT3SAS_TIMESYNC_UNIT_MASK (0x80) /* bit 7 */
100 #define MPT3SAS_TIMESYNC_MASK (0x7F) /* 0 - 6 bits */
103 #define MPT3SAS_COREDUMP_LOOP_DONE (0xFF)
104 #define MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP (0x81)
151 #define MPI3_HIM_MASK 0xFFFFFFFF /* mask every bit*/
153 #define MPT3SAS_INVALID_DEVICE_HANDLE 0xFFFF
170 #define NVME_TASK_MNGT_CUSTOM_MASK (0x0010)
195 #define MPT2_WARPDRIVE_LOGENTRY (0x8002)
[all …]

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