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/linux/Documentation/devicetree/bindings/edac/
H A Ddmc-520.yaml58 reg = <0x200000 0x80000>;
59 interrupts = <0x0 0x349 0x4>, <0x0 0x34B 0x4>;
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dhw.c29 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); in rtl92de_read_dword_dbi()
41 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); in rtl92de_write_dword_dbi()
43 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); in rtl92de_write_dword_dbi()
59 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92de_enable_bcn_sub_func()
64 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92de_disable_bcn_sub_func()
99 (union aci_aifsn *)(&(mac->ac[0].aifs)); in rtl92de_set_hw_reg()
103 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92de_set_hw_reg()
139 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", in rtl92de_set_hw_reg()
145 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92de_set_hw_reg()
146 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92de_set_hw_reg()
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/linux/arch/powerpc/platforms/powermac/
H A Dsmp.c77 #define HAMMERHEAD_BASE 0xf8000000
78 #define HHEAD_CONFIG 0x90
79 #define HHEAD_SEC_INTR 0xc0
83 #define PSURGE_PRI_INTR 0xf3019000
87 #define PSURGE_START 0xf2800000
90 #define PSURGE_QUAD_REG_ADDR 0xf8800000
92 #define PSURGE_QUAD_IRQ_SET 0
103 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
116 #define PSURGE_DUAL 0
135 if (cpu == 0) in psurge_set_ipi()
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/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dhw.c46 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl8723e_stop_tx_beacon()
48 tmp1byte &= ~(BIT(0)); in _rtl8723e_stop_tx_beacon()
59 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl8723e_resume_tx_beacon()
67 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl8723e_enable_bcn_sub_func()
72 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl8723e_disable_bcn_sub_func()
99 val_rcr &= 0x00070000; in rtl8723e_get_hw_reg()
142 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl8723e_set_hw_reg()
149 u16 b_rate_cfg = ((u16 *)val)[0]; in rtl8723e_set_hw_reg()
150 u8 rate_index = 0; in rtl8723e_set_hw_reg()
152 b_rate_cfg = b_rate_cfg & 0x15f; in rtl8723e_set_hw_reg()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dhw.c42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ce_stop_tx_beacon()
44 tmp1byte &= ~(BIT(0)); in _rtl92ce_stop_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ce_resume_tx_beacon()
57 tmp1byte |= BIT(0); in _rtl92ce_resume_tx_beacon()
63 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92ce_enable_bcn_sub_func()
68 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92ce_disable_bcn_sub_func()
95 val_rcr &= 0x00070000; in rtl92ce_get_hw_reg()
138 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92ce_set_hw_reg()
145 u16 rate_cfg = ((u16 *) val)[0]; in rtl92ce_set_hw_reg()
146 u8 rate_index = 0; in rtl92ce_set_hw_reg()
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/linux/arch/loongarch/include/asm/
H A Dloongarch.h23 #define REG_ZERO 0x0
24 #define REG_RA 0x1
25 #define REG_TP 0x2
26 #define REG_SP 0x3
27 #define REG_A0 0x4 /* Reused as V0 for return value */
28 #define REG_A1 0x5 /* Reused as V1 for return value */
29 #define REG_A2 0x6
30 #define REG_A3 0x7
31 #define REG_A4 0x8
32 #define REG_A5 0x9
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_n.c28 radio_type##_##jspace##0 : \
34 radio_type##_##jspace##0 : \
42 radio_type##_##jspace##0##_##reg_name : \
47 radio_type##_##jspace##0##_##reg_name : \
53 radio_type##_##reg_name##_##jspace##0 : \
58 radio_type##_##reg_name##_##jspace##0 : \
107 #define NPHY_RSSICAL_NB_TARGET 0
120 #define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f)))
129 #define NPHY_N_GCTL 0x66
135 #define NPHY_PAPD_COMP_OFF 0
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