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/linux/Documentation/trace/
H A Dfprobetrace.rst40 can be probed simultaneously, or 0 for the default value
48 $stackN : Fetch Nth entry of stack (N >= 0)
62 (\*2) only for the probe on function entry (offs == 0). Note, this argument access
102 field:unsigned short common_type; offset:0; size:2; signed:0;
103 field:unsigned char common_flags; offset:2; size:1; signed:0;
104 field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
107 field:unsigned long __probe_ip; offset:8; size:8; signed:0;
108 field:u64 count; offset:16; size:8; signed:0;
109 field:u64 pos; offset:24; size:8; signed:0;
111 print fmt: "(%lx) count=%Lu pos=0x%Lx", REC->__probe_ip, REC->count, REC->pos
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dlboxre2.h12 #define IRQ_CF1 evt2irq(0x320) /* CF1 */
13 #define IRQ_CF0 evt2irq(0x340) /* CF0 */
14 #define IRQ_INTD evt2irq(0x360) /* INTD */
15 #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
16 #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
17 #define IRQ_INTA evt2irq(0x3c0) /* INTA */
/linux/drivers/pmdomain/renesas/
H A Dr8a77965-sysc.c18 { "always-on", 0, 0, R8A77965_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
19 { "ca57-scu", 0x1c0, 0, R8A77965_PD_CA57_SCU, R8A77965_PD_ALWAYS_ON,
21 { "ca57-cpu0", 0x80, 0, R8A77965_PD_CA57_CPU0, R8A77965_PD_CA57_SCU,
23 { "ca57-cpu1", 0x80, 1, R8A77965_PD_CA57_CPU1, R8A77965_PD_CA57_SCU,
25 { "cr7", 0x240, 0, R8A77965_PD_CR7, R8A77965_PD_ALWAYS_ON },
26 { "a3vc", 0x380, 0, R8A77965_PD_A3VC, R8A77965_PD_ALWAYS_ON },
27 { "a3vp", 0x340, 0, R8A77965_PD_A3VP, R8A77965_PD_ALWAYS_ON },
28 { "a2vc1", 0x3c0, 1, R8A77965_PD_A2VC1, R8A77965_PD_A3VC },
29 { "3dg-a", 0x100, 0, R8A77965_PD_3DG_A, R8A77965_PD_ALWAYS_ON },
30 { "3dg-b", 0x100, 1, R8A77965_PD_3DG_B, R8A77965_PD_3DG_A },
[all …]
H A Dr8a774b1-sysc.c18 { "always-on", 0, 0, R8A774B1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
19 { "ca57-scu", 0x1c0, 0, R8A774B1_PD_CA57_SCU, R8A774B1_PD_ALWAYS_ON,
21 { "ca57-cpu0", 0x80, 0, R8A774B1_PD_CA57_CPU0, R8A774B1_PD_CA57_SCU,
23 { "ca57-cpu1", 0x80, 1, R8A774B1_PD_CA57_CPU1, R8A774B1_PD_CA57_SCU,
25 { "a3vc", 0x380, 0, R8A774B1_PD_A3VC, R8A774B1_PD_ALWAYS_ON },
26 { "a3vp", 0x340, 0, R8A774B1_PD_A3VP, R8A774B1_PD_ALWAYS_ON },
27 { "a2vc1", 0x3c0, 1, R8A774B1_PD_A2VC1, R8A774B1_PD_A3VC },
28 { "3dg-a", 0x100, 0, R8A774B1_PD_3DG_A, R8A774B1_PD_ALWAYS_ON },
29 { "3dg-b", 0x100, 1, R8A774B1_PD_3DG_B, R8A774B1_PD_3DG_A },
35 .extmask_offs = 0x2f8,
[all …]
H A Dr8a774e1-sysc.c17 { "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
19 { "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
20 { "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
21 { "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
22 { "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
23 { "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
24 { "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
25 { "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
26 { "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
[all …]
H A Dr8a7795-sysc.c17 { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
20 { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
22 { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
24 { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
26 { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
28 { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
30 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
32 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
34 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
[all …]
/linux/arch/sh/include/mach-landisk/mach/
H A Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0)
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4)
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310)
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319)
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c)
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324)
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Damlogic,meson-pinctrl-g12a-periphs.yaml24 "^bank@[0-9a-f]+$":
57 reg = <0x40 0x4c>,
58 <0xe8 0x18>,
59 <0x120 0x18>,
60 <0x2c0 0x40>,
61 <0x340 0x1c>;
65 gpio-ranges = <&periphs_pinctrl 0 0 86>;
/linux/arch/sh/include/mach-se/mach/
H A Dse7721.h16 #define PA_ROM 0xa0000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
18 #define PA_FROM 0xa1000000 /* Flash-ROM */
19 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
20 #define PA_EXT1 0xa4000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
23 #define PA_SDRAM_SIZE 0x04000000
25 #define PA_EXT4 0xb0000000
26 #define PA_EXT4_SIZE 0x04000000
[all …]
H A Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsi2.h24 CSI2_PIX_FMT_OTHERS = 0,
25 CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
26 CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
27 CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
28 CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
29 CSI2_PIX_FMT_RAW8 = 0x2a,
30 CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
31 CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
32 CSI2_PIX_FMT_RAW8_VP = 0x12a,
33 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Dp54usb.h19 #define NET2280_BASE 0x10000000
20 #define NET2280_BASE2 0x20000000
30 #define NET2280_CLK_STOP (0 << LOCAL_CLOCK_FREQUENCY)
44 #define NET2280_DEVINIT 0x00
45 #define NET2280_USBIRQENB1 0x24
46 #define NET2280_IRQSTAT1 0x2c
47 #define NET2280_FIFOCTL 0x38
48 #define NET2280_GPIOCTL 0x50
49 #define NET2280_RELNUM 0x88
50 #define NET2280_EPA_RSP 0x324
[all …]
/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_dc.c39 .regs_offset = 0x40,
40 .id = 0,
42 .cfgs_offset = 0x2c,
48 .clut_offset = 0x400,
53 .min_width = 0,
54 .min_height = 0,
57 .max_spw = 0x3f,
58 .max_vpw = 0x3f,
59 .max_hpw = 0xff,
70 .regs_offset = 0x40,
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_ppe_regs.h7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
[all …]
/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
/linux/arch/powerpc/kernel/
H A Dexceptions-64e.S39 #define SPECIAL_EXC_SRR0 0
83 lwz r12,0(r11)
119 li r10,0
145 lwz r12,0(r11)
164 PPC_TLBILX_ALL(0,R0)
200 stdcx. r0,0,r1 /* to clear the reservation */
228 REST_GPR(0, r1)
264 cmpdi cr1,r1,0; /* check if SP makes sense */ \
368 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
385 ZEROIZE_GPR(0); \
[all …]

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