Home
last modified time | relevance | path

Searched +full:0 +full:x33800000 (Results 1 – 11 of 11) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfsl,imx6q-pcie-ep.yaml134 reg = <0x33800000 0x100000>,
135 <0x18000000 0x8000000>,
136 <0x33900000 0x100000>,
137 <0x33b00000 0x100000>;
/freebsd/lib/msun/src/
H A Ds_log1pf.c22 ln2_hi = 6.9313812256e-01, /* 0x3f317180 */
23 ln2_lo = 9.0580006145e-06, /* 0x3717f7d1 */
24 two25 = 3.355443200e+07, /* 0x4c000000 */
43 ax = hx&0x7fffffff; in log1pf()
46 if (hx < 0x3ed413d0) { /* 1+x < sqrt(2)+ */ in log1pf()
47 if(ax>=0x3f800000) { /* x <= -1.0 */ in log1pf()
51 if(ax<0x38000000) { /* |x| < 2**-15 */ in log1pf()
53 &&ax<0x33800000) /* |x| < 2**-24 */ in log1pf()
58 if(hx>0||hx<=((int32_t)0xbe95f619)) { in log1pf()
59 k=0;f=x;hu=1;} /* sqrt(2)/2- <= 1+x < sqrt(2)+ */ in log1pf()
[all …]
H A Ds_erff.c26 erx = 8.42697144e-01, /* 0x3f57bb00 */
28 * In the domain [0, 2**-14], only the first term in the power series
32 efx = 1.28379166e-01, /* 0x3e0375d4 */
33 efx8= 1.02703333e+00, /* 0x3f8375d4 */
35 * Domain [0, 0.84375], range ~[-5.4419e-10, 5.5179e-10]:
38 pp0 = 1.28379166e-01, /* 0x3e0375d4 */
39 pp1 = -3.36030394e-01, /* 0xbeac0c2d */
40 pp2 = -1.86261395e-03, /* 0xbaf422f4 */
41 qq1 = 3.12324315e-01, /* 0x3e9fe8f9 */
42 qq2 = 2.16070414e-02, /* 0x3cb10140 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7d.dtsi17 cpu0: cpu@0 {
53 opp-supported-hw = <0xd>, <0x7>;
61 opp-supported-hw = <0xc>, <0x7>;
69 opp-supported-hw = <0x8>, <0x3>;
78 #phy-cells = <0>;
84 reg = <0x3007d000 0x100
[all...]
/freebsd/contrib/arm-optimized-routines/math/test/rtest/
H A Ddotest.c21 #if MPFR_VERSION < MPFR_VERSION_NUM(4, 2, 0)
102 uint32 exp = (hl >> 52) & 0x7ff; in set_mpfr_d()
105 if (exp == 0x7ff) { in set_mpfr_d()
106 if (mantissa == 0) in set_mpfr_d()
110 } else if (exp == 0 && mantissa == 0) { in set_mpfr_d()
111 mpfr_set_ui(x, 0, GMP_RNDN); in set_mpfr_d()
112 mpfr_setsign(x, x, sign < 0, GMP_RNDN); in set_mpfr_d()
114 if (exp != 0) in set_mpfr_d()
118 mpfr_set_sj_2exp(x, mantissa * sign, (int)exp - 0x3ff - 52, GMP_RNDN); in set_mpfr_d()
123 uint32 exp = (f >> 23) & 0xff; in set_mpfr_f()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mp.dtsi48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
[all …]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
206 let hasSideEffects = 0, Predicates = [HasExtLASX] in {
208 let mayLoad = 0, mayStore = 0 in {
209 def XVADD_B : LASX3R_XXX<0x740a0000>;
210 def XVADD_H : LASX3R_XXX<0x740a8000>;
211 def XVADD_W : LASX3R_XXX<0x740b0000>;
212 def XVADD_D : LASX3R_XXX<0x740b8000>;
213 def XVADD_Q : LASX3R_XXX<0x752d0000>;
215 def XVSUB_B : LASX3R_XXX<0x740c0000>;
216 def XVSUB_H : LASX3R_XXX<0x740c8000>;
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]