Home
last modified time | relevance | path

Searched +full:0 +full:x3300000 (Results 1 – 13 of 13) sorted by relevance

/linux/arch/arm64/boot/dts/qcom/
H A Dqcs8550.dtsi40 * 0x80000000 +-------------------+
44 * 0x8a800000 +-------------------+
48 * 0xa7000000 +-------------------+
52 * 0xd4d00000 +-------------------+
56 * 0x100000000 +-------------------+
60 reg = <0x0 0x81c00000 0x0 0x60000>;
66 reg = <0x0 0x81c60000 0x0 0x20000>;
72 reg = <0x0 0x81c80000 0x0 0x20000>;
77 reg = <0x0 0x81d00000 0x0 0x200000>;
83 reg = <0x0 0x81f00000 0x0 0x20000>;
[all …]
H A Dsm8550-samsung-q5q.dts39 reg = <0x0 0xb8000000 0x0 0x2b00000>;
49 pinctrl-0 = <&volume_up_n>;
73 reg = <0x0 0x9ea00000 0x0 0x59b4000>;
78 reg = <0 0x9c900000 0 0x2000000>;
83 reg = <0x0 0xd4d00000 0x0 0x3300000>;
88 reg = <0x0 0x8b400000 0x0 0xfc00000>;
93 reg = <0x0 0xd4a80000 0x0 0x280000>;
102 reg = <0x0 0xb8000000 0x0 0x2b00000>;
109 regulators-0 {
515 pinctrl-0 = <&pcie0_default_state>;
H A Dsdm630.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
55 reg = <0x0 0x100>;
75 reg = <0x0 0x101>;
90 reg = <0x0 0x102>;
105 reg = <0x0 0x103>;
117 CPU4: cpu@0 {
120 reg = <0x0 0x0>;
140 reg = <0x0 0x1>;
[all …]
H A Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sc7280-lpasscorecc.yaml136 reg = <0x3300000 0x30000>,
137 <0x32a9000 0x1000>;
154 reg = <0x3c00000 0x28>;
168 reg = <0x3900000 0x50000>;
183 reg = <0x3380000 0x30000>;
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8026-asus-sparrow.dts17 qcom,msm-id = <199 0x20000>;
22 reg = <0x02f00000 0x100000>;
26 reg = <0x3100000 0x200000>;
30 reg = <0x3300000 0x600000>;
34 reg = <0x3900000 0x1400000>;
38 reg = <0x4d00000 0x1b00000>;
42 reg = <0x7f00000 0x100000>;
58 pinctrl-0 = <&wlan_regulator_default_state>;
70 pinctrl-0 = <&blsp1_uart1_default_state>;
77 pinctrl-0 = <&bluetooth_default_state>;
[all …]
H A Dqcom-apq8026-huawei-sturgeon.dts18 qcom,msm-id = <199 0x20000>;
23 reg = <0x02f00000 0x100000>;
28 reg = <0x3100000 0x200000>;
33 reg = <0x3300000 0x600000>;
38 reg = <0x3900000 0x1400000>;
43 reg = <0x4d00000 0x1b00000>;
48 reg = <0x7f00000 0x100000>;
64 pinctrl-0 = <&wlan_regulator_default_state>;
79 reg = <0x5a>;
87 pinctrl-0 = <&vibrator_default_state>;
[all …]
/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.c15 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
19 #define CRB_BLK(off) ((off >> 20) & 0x3f)
20 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
21 #define CRB_WINDOW_2M (0x130060)
22 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
23 #define CRB_INDIRECT_2M (0x1e0000UL)
52 {{{0, 0, 0, 0} } }, /* 0: PCI */
53 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
54 {1, 0x0110000, 0x0120000, 0x130000},
55 {1, 0x0120000, 0x0122000, 0x124000},
[all …]
/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hw.c16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
18 #define MS_WIN(addr) (addr & 0x0ffc0000)
22 #define CRB_BLK(off) ((off >> 20) & 0x3f)
23 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
24 #define CRB_WINDOW_2M (0x130060)
25 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
26 #define CRB_INDIRECT_2M (0x1e0000UL)
57 {{{0, 0, 0, 0} } }, /* 0: PCI */
58 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_nx.c15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define BLOCK_PROTECT_BITS 0x0F
[all …]
/linux/drivers/scsi/qla4xxx/
H A Dql4_nx.c18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
[all …]