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/linux/Documentation/devicetree/bindings/gpio/
H A Drealtek,otto-gpio.yaml24 pattern: "^gpio@[0-9a-f]+$"
86 reg = <0x3500 0x1c>;
98 reg = <0x3300 0x1c>, <0x3338 0x8>;
/linux/drivers/soc/vt8500/
H A Dwmt-socinfo.c19 { "VT8420", 0x3300 },
20 { "VT8430", 0x3357 },
21 { "VT8500", 0x3400 },
24 { "WM8425", 0x3429 },
25 { "WM8435", 0x3437 },
26 { "WM8440", 0x3451 },
27 { "WM8505", 0x3426 },
28 { "WM8650", 0x3465 },
29 { "WM8750", 0x3445 },
30 { "WM8850", 0x3481 },
[all …]
/linux/lib/crc/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
H A Darizona-core.c38 int ret = 0; in arizona_clk32k_enable()
48 if (ret != 0) in arizona_clk32k_enable()
51 if (ret != 0) { in arizona_clk32k_enable()
58 if (ret != 0) in arizona_clk32k_enable()
69 if (ret != 0) in arizona_clk32k_enable()
82 WARN_ON(arizona->clk32k_ref <= 0); in arizona_clk32k_disable()
86 if (arizona->clk32k_ref == 0) { in arizona_clk32k_disable()
88 ARIZONA_CLK_32K_ENA, 0); in arizona_clk32k_disable()
103 return 0; in arizona_clk32k_disable()
124 if (ret != 0) { in arizona_underclocked()
[all …]
/linux/arch/mips/boot/dts/realtek/
H A Drtl930x.dtsi16 #address-cells = <0>;
23 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 reg = <0x1b000000 0x10000>;
57 reg = <0x0c 0x4>;
58 value = <0x01>;
63 reg = <0x36c 0x14>;
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x404
[all …]
/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c103 u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0; in gt215_link_train_calc()
105 for (i = 0; i < 8; i++) { in gt215_link_train_calc()
106 for (lo = 0; lo < 0x40; lo++) { in gt215_link_train_calc()
107 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
109 if (vals[lo] & (0x101 << i)) in gt215_link_train_calc()
113 if (lo == 0x40) in gt215_link_train_calc()
116 for (hi = lo + 1; hi < 0x40; hi++) { in gt215_link_train_calc()
117 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
119 if (!(vals[hi] & (0x101 << i))) { in gt215_link_train_calc()
126 bins[(median[i] & 0xf0) >> 4]++; in gt215_link_train_calc()
[all …]
/linux/drivers/hwmon/
H A Djc42.c27 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
30 #define JC42_REG_CAP 0x00
31 #define JC42_REG_CONFIG 0x01
32 #define JC42_REG_TEMP_UPPER 0x02
33 #define JC42_REG_TEMP_LOWER 0x03
34 #define JC42_REG_TEMP_CRITICAL 0x04
35 #define JC42_REG_TEMP 0x05
36 #define JC42_REG_MANID 0x06
37 #define JC42_REG_DEVICEID 0x07
38 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc-ctrl.c41 #define GET_STATUS_B00 0x0B00
42 #define SENSOR_TYPE_FORMATTER1 0x0C00
43 #define GET_STATUS_3000 0x3000
44 #define READ_RAW_Y_MEAN_FORMATTER 0x3100
45 #define SET_POWER_SAVE_MODE_FORMATTER 0x3200
46 #define MIRROR_IMAGE_FORMATTER 0x3300
47 #define LED_FORMATTER 0x3400
48 #define LOWLIGHT 0x3500
49 #define GET_STATUS_3600 0x3600
50 #define SENSOR_TYPE_FORMATTER2 0x3700
[all …]
/linux/sound/soc/renesas/rcar/
H A Dsrc.c52 for ((i) = 0; \
70 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_activation()
77 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_halt()
99 return 0; in rsnd_src_convert_rate()
121 unsigned int rate = 0; in rsnd_src_get_rate()
149 0x01800000, /* 6 - 1/6 */
150 0x01000000, /* 6 - 1/4 */
151 0x00c00000, /* 6 - 1/3 */
152 0x00800000, /* 6 - 1/2 */
153 0x0060000
[all...]
/linux/drivers/net/ethernet/smsc/
H A Dsmc91x.c15 * nowait = 0 for normal wait states, 1 eliminates additional wait states
52 #define SMC_DEBUG 0
88 # define SMC_NOWAIT 0
137 #define THROTTLE_TX_PKTS 0
149 } while (0)
153 if (SMC_DEBUG > 0) \
157 } while (0)
169 for (i = 0; i < lines ; i ++) { in PRINT_PKT()
172 for (cur = 0; cur < 8; cur++) { in PRINT_PKT()
181 for (i = 0; i < remainder/2 ; i++) { in PRINT_PKT()
[all …]
H A Dsmc9194.c17 . ifport = 0 for autodetect, 1 for TP, 2 for AUI ( or 10base2 )
110 {.port = 0x200, .irq = 0},
111 {.port = 0x220, .irq = 0},
112 {.port = 0x240, .irq = 0},
113 {.port = 0x260, .irq = 0},
114 {.port = 0x280, .irq = 0},
115 {.port = 0x2A0, .irq = 0},
116 {.port = 0x2C0, .irq = 0},
117 {.port = 0x2E0, .irq = 0},
118 {.port = 0x300, .irq = 0},
[all …]
H A Dsmc91x.h38 } while (0)
73 ({ BUG(); 0; }); \
87 } while (0)
104 v |= readl(ioaddr + (reg & ~2)) & 0xffff; in _SMC_outw_align4()
140 #define SMC_CAN_USE_8BIT 0
142 #define SMC_CAN_USE_32BIT 0
148 while (l-- > 0) in mcf_insw()
155 while (l-- > 0) in mcf_outsw()
164 #define SMC_IRQ_FLAGS 0
279 DMA_DEV_TO_MEM, 0); in smc_pxa_dma_inpump()
[all …]
/linux/drivers/soc/fsl/qbman/
H A Dbman.c40 #define BM_REG_RCR_PI_CINH 0x3000
41 #define BM_REG_RCR_CI_CINH 0x3100
42 #define BM_REG_RCR_ITR 0x3200
43 #define BM_REG_CFG 0x3300
44 #define BM_REG_SCN(n) (0x3400 + ((n) << 6))
45 #define BM_REG_ISR 0x3e00
46 #define BM_REG_IER 0x3e40
47 #define BM_REG_ISDR 0x3e80
48 #define BM_REG_IIR 0x3ec0
51 #define BM_CL_CR 0x0000
[all …]
H A Dqman.c40 #define QMAN_ITP_MAX 0xFFF
48 #define QM_REG_EQCR_PI_CINH 0x3000
49 #define QM_REG_EQCR_CI_CINH 0x3040
50 #define QM_REG_EQCR_ITR 0x3080
51 #define QM_REG_DQRR_PI_CINH 0x3100
52 #define QM_REG_DQRR_CI_CINH 0x3140
53 #define QM_REG_DQRR_ITR 0x3180
54 #define QM_REG_DQRR_DCAP 0x31C0
55 #define QM_REG_DQRR_SDQCR 0x3200
56 #define QM_REG_DQRR_VDQCR 0x3240
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_mfw_hsi.h9 #define MFW_TRACE_SIGNATURE 0x25071946
12 #define MFW_TRACE_EVENTID_MASK 0x00ffff
13 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
22 * 0 - just errors will be written to the buffer
24 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
53 #define OFFSIZE_OFFSET_SHIFT 0
54 #define OFFSIZE_OFFSET_MASK 0x0000ffff
57 #define OFFSIZE_SIZE_MASK 0xffff0000
77 #define ETH_SPEED_AUTONEG 0x0
78 #define ETH_SPEED_SMARTLINQ 0x8
[all …]
/linux/sound/soc/codecs/
H A Drt5682s.c32 #define DEVICE_ID 0x6749
50 {RT5682S_I2C_CTRL, 0x0007},
51 {RT5682S_DIG_IN_CTRL_1, 0x0000},
52 {RT5682S_CHOP_DAC_2, 0x2020},
53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
55 {RT5682S_HP_CALIB_CTRL_9, 0x0002},
56 {RT5682S_DEPOP_1, 0x0000},
57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
58 {RT5682S_DAC1_DIG_VOL, 0xfefe},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]

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