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Searched +full:0 +full:x32c00000 (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,secure-proxy.yaml22 pattern: "^mailbox@[0-9a-f]+$"
45 pattern: "^rx_[0-9]{3}$"
74 reg = <0x32c00000 0x100000>,
75 <0x32400000 0x100000>,
76 <0x32800000 0x100000>;
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
H A Dimx8mn.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mp.dtsi48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
H A Dk3-j7200-main.dtsi10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
37 reg = <0x4080 0x20>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
[all …]
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
H A Dk3-j784s4-main.dtsi16 #clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x4034 0x4>;
[all …]