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/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_fbc_regs.h9 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
10 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
11 #define FBC_CONTROL _MMIO(0x3208)
21 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
23 #define FBC_COMMAND _MMIO(0x320c)
24 #define FBC_CMD_COMPRESS REG_BIT(0)
25 #define FBC_STATUS _MMIO(0x3210)
29 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
30 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
33 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Drealtek,otto-timer.yaml18 pattern: "^timer@[0-9a-f]+$"
57 reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
58 <0x3230 0x10>, <0x3240 0x10>;
/linux/drivers/net/ethernet/intel/ixgbevf/
H A Dregs.h7 #define IXGBE_VFCTRL 0x00000
8 #define IXGBE_VFSTATUS 0x00008
9 #define IXGBE_VFLINKS 0x00010
10 #define IXGBE_VFFRTIMER 0x00048
11 #define IXGBE_VFRXMEMWRAP 0x03190
12 #define IXGBE_VTEICR 0x00100
13 #define IXGBE_VTEICS 0x00104
14 #define IXGBE_VTEIMS 0x00108
15 #define IXGBE_VTEIMC 0x0010C
16 #define IXGBE_VTEIAC 0x00110
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x404
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-dreambox.c22 { 0x3200, KEY_POWER },
25 { 0x3290, KEY_HELP },
28 { 0x3201, KEY_1 },
29 { 0x3202, KEY_2 },
30 { 0x3203, KEY_3 },
31 { 0x3204, KEY_4 },
32 { 0x3205, KEY_5 },
33 { 0x3206, KEY_6 },
34 { 0x3207, KEY_7 },
35 { 0x3208, KEY_8 },
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8996-qmp-pcie-phy.yaml57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-ucc-qmc.yaml65 const: 0
68 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
83 minimum: 0
156 reg = <0x3200 0x200>,
157 <0x10000 0x1000>;
164 #size-cells = <0>;
173 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
174 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
182 fsl,tx-ts-mask = <0x00000000 0x00000055>;
183 fsl,rx-ts-mask = <0x00000000 0x00000055>;
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dpolaris10_smumgr.c55 #define POLARIS10_SMC_SIZE 0x20000
58 #define MC_CG_ARB_FREQ_F1 0x0b
63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
83 …0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000…
84 …0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000…
85 …0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000…
86 …0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000…
87 …0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100…
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569si-post.dtsi39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
43 /* controller at 0xa000 */
49 bus-range = <0 255>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
54 pcie@0 {
55 reg = <0 0 0 0 0>;
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal1.h16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS 0x00
18 #define MV88E6352_G1_STS_PPU_STATE 0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
34 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Despi.c47 #define TRICN_CMD_READ 0x11
48 #define TRICN_CMD_WRITE 0x21
62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
86 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init()
87 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init()
88 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init()
91 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init()
93 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init()
95 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init()
96 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc836x_rdk.dts32 #size-cells = <0>;
34 PowerPC,8360@0 {
36 reg = <0>;
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
51 reg = <0 0>;
60 ranges = <0 0xe0000000 0x200000>;
61 reg = <0xe0000000 0x200>;
63 bus-frequency = <0>;
[all …]
H A Dkmeter1.dts29 #size-cells = <0>;
31 PowerPC,8360@0 {
33 reg = <0x0>;
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 bus-frequency = <0>; /* Filled in by U-Boot */
40 clock-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0 0>; /* Filled in by U-Boot */
54 ranges = <0x0 0xe0000000 0x00200000>;
55 reg = <0xe0000000 0x00000200>;
56 bus-frequency = <0>; /* Filled in by U-Boot */
[all …]
/linux/sound/soc/codecs/
H A Drt711-sdca-sdw.c22 case 0x201a ... 0x2027: in rt711_sdca_readable_register()
23 case 0x2029 ... 0x202a: in rt711_sdca_readable_register()
24 case 0x202d ... 0x2034: in rt711_sdca_readable_register()
25 case 0x2200 ... 0x2204: in rt711_sdca_readable_register()
26 case 0x2206 ... 0x2212: in rt711_sdca_readable_register()
27 case 0x2220 ... 0x2223: in rt711_sdca_readable_register()
28 case 0x2230 ... 0x2239: in rt711_sdca_readable_register()
29 case 0x2f01 ... 0x2f0f: in rt711_sdca_readable_register()
30 case 0x2f30 ... 0x2f36: in rt711_sdca_readable_register()
31 case 0x2f50 ... 0x2f5a: in rt711_sdca_readable_register()
[all …]
/linux/arch/powerpc/kernel/
H A Dhead_85xx.S71 li r25,0 /* phys kernel start (low) */
72 li r24,0 /* CPU number */
73 li r23,0 /* phys kernel start (high) */
84 0: mflr r8
85 addis r3,r8,(is_second_reloc - 0b)@ha
86 lwz r19,(is_second_reloc - 0b)@l(r3)
103 addis r4,r8,(kernstart_addr - 0b)@ha
104 addi r4,r4,(kernstart_addr - 0b)@l
107 addis r6,r8,(memstart_addr - 0b)@ha
108 addi r6,r6,(memstart_addr - 0b)@l
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc-ctrl.c41 #define GET_STATUS_B00 0x0B00
42 #define SENSOR_TYPE_FORMATTER1 0x0C00
43 #define GET_STATUS_3000 0x3000
44 #define READ_RAW_Y_MEAN_FORMATTER 0x3100
45 #define SET_POWER_SAVE_MODE_FORMATTER 0x3200
46 #define MIRROR_IMAGE_FORMATTER 0x3300
47 #define LED_FORMATTER 0x3400
48 #define LOWLIGHT 0x3500
49 #define GET_STATUS_3600 0x3600
50 #define SENSOR_TYPE_FORMATTER2 0x3700
[all …]
/linux/drivers/ata/
H A Dpata_icside.c16 #define ICS_IDENT_OFFSET 0x2280
18 #define ICS_ARCIN_V5_INTRSTAT 0x0000
19 #define ICS_ARCIN_V5_INTROFFSET 0x0004
21 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
22 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
23 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
24 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
33 .dataoffset = 0x2800,
34 .ctrloffset = 0x2b80,
39 .dataoffset = 0x2000,
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7629.c12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
[all …]
/linux/drivers/media/tuners/
H A Dxc4000.c29 MODULE_PARM_DESC(debug, "Debugging level (0 to 2, default: 0 (off)).");
33 MODULE_PARM_DESC(no_poweroff, "Power management (1: disabled, 2: enabled, 0 (default): use device-s…
46 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
107 #define XC_POWERED_DOWN 0x80000000U
110 #define XC_RF_MODE_AIR 0
114 #define XC_PRODUCT_ID_FW_NOT_LOADED 0x2000
115 #define XC_PRODUCT_ID_XC4000 0x0FA0
116 #define XC_PRODUCT_ID_XC4100 0x1004
119 #define XREG_INIT 0x00
120 #define XREG_VIDEO_MODE 0x01
[all …]
/linux/drivers/soc/fsl/qbman/
H A Dbman.c40 #define BM_REG_RCR_PI_CINH 0x3000
41 #define BM_REG_RCR_CI_CINH 0x3100
42 #define BM_REG_RCR_ITR 0x3200
43 #define BM_REG_CFG 0x3300
44 #define BM_REG_SCN(n) (0x3400 + ((n) << 6))
45 #define BM_REG_ISR 0x3e00
46 #define BM_REG_IER 0x3e40
47 #define BM_REG_ISDR 0x3e80
48 #define BM_REG_IIR 0x3ec0
51 #define BM_CL_CR 0x0000
[all …]
/linux/drivers/mailbox/
H A Dmtk-cmdq-mailbox.c23 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
26 #define CMDQ_CURR_IRQ_STATUS 0x10
27 #define CMDQ_SYNC_TOKEN_UPDATE 0x68
28 #define CMDQ_THR_SLOT_CYCLES 0x30
29 #define CMDQ_THR_BASE 0x100
30 #define CMDQ_THR_SIZE 0x80
31 #define CMDQ_THR_WARM_RESET 0x00
32 #define CMDQ_THR_ENABLE_TASK 0x04
33 #define CMDQ_THR_SUSPEND_TASK 0x08
34 #define CMDQ_THR_CURR_STATUS 0x0c
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]

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