Searched +full:0 +full:x30c000 (Results 1 – 3 of 3) sorted by relevance
32 interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96.52 reg = <0x300000 0x4000>, <0x304000 0x4000>, <0x308000 0x4000>, <0x30C000 0x4000>;
41 reg = <0x0 0x4000000 0x0 0x200000>;46 reg = <0 0x4400000 0 0x1000000>;77 ranges = <0x0 0x0 0xf0000000 0x1000000>;81 reg = <0x100000 0x100000>;105 reg = <0x210000 0x10000>,106 <0x220000 0x20000>,107 <0x240000 0x20000>,108 <0x260000 0x20000>;113 reg = <0x280000 0x1000>;120 reg = <0x290000 0x1000>;[all …]
23 #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE 0x20000024 #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE 0x1000027 #define REG_NPU_LOCAL_SRAM 0x029 #define NPU_PC_BASE_ADDR 0x30500030 #define REG_PC_DBG(_n) (0x305000 + ((_n) * 0x100))32 #define NPU_CLUSTER_BASE_ADDR 0x30600034 #define REG_CR_BOOT_TRIGGER (NPU_CLUSTER_BASE_ADDR + 0x000)35 #define REG_CR_BOOT_CONFIG (NPU_CLUSTER_BASE_ADDR + 0x004)36 #define REG_CR_BOOT_BASE(_n) (NPU_CLUSTER_BASE_ADDR + 0x020 + ((_n) << 2))38 #define NPU_MBOX_BASE_ADDR 0x30c000[all …]