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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/ti/
H A Dk3-udma.yaml56 for source thread IDs (rx): 0 - 0x7fff
57 for destination thread IDs (tx): 0x8000 - 0xffff
164 ranges = <0x0 0x30800000 0x0 0x30800000
[all...]
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Datanf_2u9.c12 #define PiOver2 0x1.921fb6p+0f
13 #define AbsMask 0x7fffffff
14 #define TinyBound 0x30800000 /* asuint(0x1p-30). */
15 #define BigBound 0x4e800000 /* asuint(0x1p30). */
16 #define One 0x3f800000
19 atan(x) ~ shift + z + z^3 * P(z^2) with reduction to [0,1]
22 atanf(0x1.0565ccp+0) got 0x1.97771p-1
23 want 0x1.97770ap-1. */
37 if (ia > 0x7f800000) in atanf()
58 shift = 0; in atanf()
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/advsimd/
H A Dasinhf.c24 .big_bound = V4 (0x5f800000), /* asuint(0x1p64). */
26 .tiny_bound = V4 (0x30800000) /* asuint(0x1p-30). */
43 _ZGVnN4v_asinhf(0x1.d86124p-3) got 0x1.d449bep-3
44 want 0x1.d449c4p-3. */
82 TEST_INTERVAL (V_NAME_F1 (asinh), 0, 0x1p-12, 40000)
83 TEST_INTERVAL (V_NAME_F1 (asinh), 0x1p-12, 1.0, 40000)
84 TEST_INTERVAL (V_NAME_F1 (asinh), 1.0, 0x1p11, 40000)
85 TEST_INTERVAL (V_NAME_F1 (asinh), 0x1p11, inf, 40000)
86 TEST_INTERVAL (V_NAME_F1 (asinh), -0, -0x1p-12, 20000)
87 TEST_INTERVAL (V_NAME_F1 (asinh), -0x1p-12, -1.0, 20000)
[all …]
H A Datanf.c21 .poly = { V4 (-0x1.55555p-2f), V4 (0x1.99935ep-3f), V4 (-0x1.24051ep-3f),
22 V4 (0x1.bd7368p-4f), V4 (-0x1.491f0ep-4f), V4 (0x1.93a2c0p-5f),
23 V4 (-0x1.4c3c60p-6f), V4 (0x1.01fd88p-8f) },
24 .pi_over_2 = V4 (0x1.921fb6p+0f),
27 #define SignMask v_u32 (0x80000000)
31 #define TinyBound 0x30800000 /* asuint(0x1p-30). */
32 #define BigBound 0x4e800000 /* asuint(0x1p30). */
43 atan(x) ~ shift + z + z^3 * P(z^2) with reduction to [0,1]
45 _ZGVnN4v_atanf (0x1.0468f6p+0) got 0x1.967f06p-1 want 0x1.967fp-1. */
57 uint32x4_t ia = vandq_u32 (ix, v_u32 (0x7ff00000)); in V_NAME_F1()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
H A Dimx8mn.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mp.dtsi48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
[all …]
/freebsd/lib/msun/src/
H A De_jnf.c23 static const volatile float vone = 1, vzero = 0;
26 two = 2.0000000000e+00, /* 0x40000000 */
27 one = 1.0000000000e+00; /* 0x3F800000 */
42 ix = 0x7fffffff&hx; in jnf()
44 if(ix>0x7f800000) return x+x; in jnf()
45 if(n<0){ in jnf()
48 hx ^= 0x80000000; in jnf()
50 if(n==0) return(j0f(x)); in jnf()
52 sgn = (n&1)&(hx>>31); /* even n -- 0, odd n -- sign(x) */ in jnf()
54 if(ix==0||ix>=0x7f800000) /* if x is 0 or inf */ in jnf()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7s.dtsi56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
94 opp-supported-hw = <0xf>, <0xf>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
116 #phy-cells = <0>;
124 #phy-cells = <0>;
143 #size-cells = <0>;
[all …]
/freebsd/sys/dev/rl/
H A Dif_rlreg.h36 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
38 #define RL_IDR2 0x0002
39 #define RL_IDR3 0x0003
40 #define RL_IDR4 0x0004
41 #define RL_IDR5 0x0005
43 #define RL_MAR0 0x0008 /* Multicast hash table */
44 #define RL_MAR1 0x0009
45 #define RL_MAR2 0x000A
46 #define RL_MAR3 0x000B
[all …]
/freebsd/sys/dev/sfxge/common/
H A Def10_tlv_layout.h59 * special values defined in the document, they are of the form 0xLTTTNNNN,
63 * 0: static configuration
100 #define TLV_TAG_END (0xEEEEEEEE)
105 #define TLV_TAG_SKIP (0x00000000)
106 #define TLV_TAG_INVALID (0xFFFFFFFF)
111 * 0.
114 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
120 /* 0 indicates the default segment (always located at offset 0), while other values
122 * The default segment may also have preset > 0, which means that it is a preset
123 * selected through an RFID command and copied by FW to the location at offset 0. */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
13 def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
16 def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
18 def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>,
20 SDTCisSameAs<0, 2>,
22 def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,
23 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
24 def SDT_loongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>,
25 SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
[all …]
/freebsd/sys/dev/bce/
H A Dif_bcefw.h40 int bce_COM_b06FwReleaseMajor = 0x6;
41 int bce_COM_b06FwReleaseMinor = 0x0;
42 int bce_COM_b06FwReleaseFix = 0xf;
43 u32 bce_COM_b06FwStartAddr = 0x08000118;
44 u32 bce_COM_b06FwTextAddr = 0x08000000;
45 int bce_COM_b06FwTextLen = 0x4a68;
46 u32 bce_COM_b06FwDataAddr = 0x00000000;
47 int bce_COM_b06FwDataLen = 0x0;
48 u32 bce_COM_b06FwRodataAddr = 0x08004a68;
49 int bce_COM_b06FwRodataLen = 0x14;
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]