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/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt6002.dtsi70 reg = <0x0 0x800>;
72 cpu-release-addr = <0 0>; /* To be filled by loader */
74 i-cache-size = <0x20000>;
75 d-cache-size = <0x10000>;
84 reg = <0x0 0x801>;
86 cpu-release-addr = <0 0>; /* To be filled by loader */
88 i-cache-size = <0x20000>;
89 d-cache-size = <0x10000>;
98 reg = <0x0 0x10900>;
100 cpu-release-addr = <0 0>; /* To be filled by loader */
[all …]
H A Dt600x-common.dtsi16 #size-cells = <0>;
59 cpu_e00: cpu@0 {
62 reg = <0x0 0x0>;
64 cpu-release-addr = <0 0>; /* To be filled by loader */
66 i-cache-size = <0x20000>;
67 d-cache-size = <0x10000>;
76 reg = <0x0 0x1>;
78 cpu-release-addr = <0 0>; /* To be filled by loader */
80 i-cache-size = <0x20000>;
81 d-cache-size = <0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
40 ranges = <0x0 0x30000 0x10000>;
41 reg = <0x30000 0x10000>;
42 interrupts = <58 2 0 0>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <45 2 0 0>;
51 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
[all …]
H A Dpq3-sec2.1-0.dtsi2 * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec2.1", "fsl,sec2.0";
37 reg = <0x30000 0x10000>;
38 interrupts = <45 2 0 0>;
41 fsl,exec-units-mask = <0xfe>;
42 fsl,descriptor-types-mask = <0x12b0ebf>;
H A Dpq3-sec3.0-0.dtsi2 * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0x9fe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
H A Dpq3-sec3.1-0.dtsi2 * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.1", "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0xbfe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
H A Dpq3-sec3.3-0.dtsi2 * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0x97c>;
44 fsl,descriptor-types-mask = <0x3a30abf>;
/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Drt2880_eval.dts10 memory@0 {
12 reg = <0x8000000 0x2000000>;
21 reg = <0x1f000000 0x400000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x3b0000>;
H A Drt3052_eval.dts10 memory@0 {
12 reg = <0x0 0x2000000>;
21 reg = <0x1f000000 0x800000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x7b0000>;
H A Dmt7621-gnubee-gb-pc1.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
57 flash@0 {
61 reg = <0>;
65 partition@0 {
67 reg = <0x0 0x3000
[all...]
H A Dmt7621-gnubee-gb-pc2.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
77 flash@0 {
81 reg = <0>;
85 partition@0 {
87 reg = <0x0 0x3000
[all...]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-dir665.dts18 reg = <0x00000000 0x8000000>; /* 128 MB */
28 pinctrl-0 =< &pmx_led_usb
81 flash@0 {
86 reg = <0>;
88 partition@0 {
90 reg = <0x0 0x30000>;
96 reg = <0x30000 0x10000>;
102 reg = <0x40000 0x180000>;
107 reg = <0x1c0000 0xe00000>;
112 reg = <0xfc0000 0x10000>;
[all …]
H A Dorion5x-linkstation.dtsi55 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
56 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
57 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
67 #size-cells = <0>;
68 pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>;
109 flash@0 {
111 reg = <0 0x40000>;
119 header@0 {
120 reg = <0 0x30000>;
125 reg = <0x30000 0xF000>;
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_dev_err.h10 #define ADF_ERRSOU0 (0x3A000 + 0x00)
11 #define ADF_ERRSOU1 (0x3A000 + 0x04)
12 #define ADF_ERRSOU2 (0x3A000 + 0x08)
13 #define ADF_ERRSOU3 (0x3A000 + 0x0C)
14 #define ADF_ERRSOU4 (0x3A000 + 0xD0)
15 #define ADF_ERRSOU5 (0x3A000 + 0xD8)
16 #define ADF_ERRMSK0 (0x3A000 + 0x10)
17 #define ADF_ERRMSK1 (0x3A000 + 0x14)
18 #define ADF_ERRMSK2 (0x3A000 + 0x18)
19 #define ADF_ERRMSK3 (0x3A000 + 0x1C)
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.h7 #define ADF_C62X_SRAM_BAR 0
11 #define ADF_C62X_TX_RINGS_MASK 0xFF
15 #define ADF_C62X_ACCELERATORS_MASK 0x1F
16 #define ADF_C62X_ACCELENGINES_MASK 0x3FF
18 #define ADF_C62X_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
19 #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
20 #define ADF_C62X_SMIA0_MASK 0xFFFF
21 #define ADF_C62X_SMIA1_MASK 0x1
22 #define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC
27 #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.h7 #define ADF_200XX_PMISC_BAR 0
10 #define ADF_200XX_TX_RINGS_MASK 0xFF
14 #define ADF_200XX_ACCELERATORS_MASK 0x7
15 #define ADF_200XX_ACCELENGINES_MASK 0x3F
17 #define ADF_200XX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
18 #define ADF_200XX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
19 #define ADF_200XX_SMIA0_MASK 0xFFFF
20 #define ADF_200XX_SMIA1_MASK 0x1
21 #define ADF_200XX_SOFTSTRAP_CSR_OFFSET 0x2EC
25 #define ADF_200XX_PFIEERRUNCSTSR 0x280
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.h7 #define ADF_C3XXX_PMISC_BAR 0
10 #define ADF_C3XXX_TX_RINGS_MASK 0xFF
14 #define ADF_C3XXX_ACCELERATORS_MASK 0x7
15 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F
17 #define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
18 #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
19 #define ADF_C3XXX_SMIA0_MASK 0xFFFF
20 #define ADF_C3XXX_SMIA1_MASK 0x1
21 #define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC
26 #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,sc7280-lpasscorecc.yaml136 reg = <0x3300000 0x30000>,
137 <0x32a9000 0x1000>;
154 reg = <0x3c00000 0x28>;
168 reg = <0x3900000 0x50000>;
183 reg = <0x338000
[all...]
H A Dqcom,turingcc.txt14 reg = <0x00800000 0x30000>;
/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.h7 #define ADF_DH895XCC_SRAM_BAR 0
11 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF
12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0
15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1
16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2
17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
24 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
[all …]
/freebsd/sys/dev/ata/chipsets/
H A Data-marvell.c66 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
68 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
89 {{ ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" }, in ata_marvell_probe()
90 { ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" }, in ata_marvell_probe()
91 { ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" }, in ata_marvell_probe()
92 { ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" }, in ata_marvell_probe()
93 { ATA_M88SE6141, 0, 4, MV_61XX, ATA_UDMA6, "88SE6141" }, in ata_marvell_probe()
94 { ATA_M88SE6145, 0, 4, MV_61XX, ATA_UDMA6, "88SE6145" }, in ata_marvell_probe()
95 { 0x91a41b4b, 0, 0, MV_91XX, ATA_UDMA6, "88SE912x" }, in ata_marvell_probe()
96 { 0, 0, 0, 0, 0, 0}}; in ata_marvell_probe()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dgmu.yaml24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
298 reg = <0x506a000 0x30000>,
299 <0xb280000 0x10000>,
300 <0xb480000 0x10000>;
323 reg = <0x0596a000 0x30000>;
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsynopsys.txt24 reg = <0xf8006000 0x1000>;
29 reg = <0x0 0xfd070000 0x0 0x30000>;
31 interrupts = <0 112 4>;
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek-vpu.txt25 reg = <0 0x10020000 0 0x30000>,
26 <0 0x10050000 0 0x100>;

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