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/linux/arch/arm64/boot/dts/ti/
H A Dk3-serdes.h13 #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
14 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
15 #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
16 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
18 #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
19 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
20 #define J721E_SERDES0_LANE1_USB3_0 0x2
21 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
23 #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
24 #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
[all …]
/linux/drivers/pinctrl/berlin/
H A Dberlin-bg4ct.c19 BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
20 BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RSTn */
21 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO47 */
22 BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
23 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */
24 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD0 */
25 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */
26 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */
27 BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06,
28 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */
[all …]
H A Dpinctrl-as370.c19 BERLIN_PINCTRL_GROUP("I2S1_BCLKIO", 0x0, 0x3, 0x00,
20 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO0 */
21 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKIO */
22 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG0 */
23 BERLIN_PINCTRL_GROUP("I2S1_LRCKIO", 0x0, 0x3, 0x03,
24 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO1 */
25 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKIO */
26 BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG1 */
27 BERLIN_PINCTRL_GROUP("I2S1_DO0", 0x0, 0x3, 0x06,
28 BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 1P8V RSTB*/
[all …]
H A Dberlin-bg2q.c20 BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00,
21 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
22 BERLIN_PINCTRL_FUNCTION(0x1, "mmc"),
23 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
24 BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03,
25 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
26 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
27 BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06,
28 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
29 BERLIN_PINCTRL_FUNCTION(0x2, "arc"),
[all …]
H A Dberlin-bg2cd.c20 BERLIN_PINCTRL_GROUP("G0", 0x00, 0x3, 0x00,
21 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
22 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
23 BERLIN_PINCTRL_FUNCTION(0x2, "led"),
24 BERLIN_PINCTRL_FUNCTION(0x3, "pwm")),
25 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x3, 0x03,
26 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
27 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
28 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
29 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
[all …]
/linux/include/dt-bindings/mux/
H A Dti-serdes.h19 #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
20 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
21 #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
22 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
24 #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
25 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
26 #define J721E_SERDES0_LANE1_USB3_0 0x2
27 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
29 #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
30 #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h11 #define IOMUXC_GPR0 0x00
12 #define IOMUXC_GPR1 0x04
13 #define IOMUXC_GPR2 0x08
14 #define IOMUXC_GPR3 0x0c
15 #define IOMUXC_GPR4 0x10
16 #define IOMUXC_GPR5 0x14
17 #define IOMUXC_GPR6 0x18
18 #define IOMUXC_GPR7 0x1c
19 #define IOMUXC_GPR8 0x20
20 #define IOMUXC_GPR9 0x24
[all …]
/linux/drivers/clk/mmp/
H A Dclk-of-pxa1928.c23 #define MPMU_UART_PLL 0x14
37 {0, "clk32", NULL, 0, 32768},
38 {0, "vctcxo", NULL, 0, 26000000},
39 {0, "pll1_624", NULL, 0, 624000000},
40 {0, "pll5p", NULL, 0, 832000000},
41 {0, "pll5", NULL, 0, 1248000000},
42 {0, "usb_pll", NULL, 0, 480000000},
46 {0, "pll1_d2", "pll1_624", 1, 2, 0},
47 {0, "pll1_d9", "pll1_624", 1, 9, 0},
48 {0, "pll1_d12", "pll1_624", 1, 12, 0},
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/linux/arch/x86/crypto/
H A Dserpent-sse2-i586-asm_32.S40 pshufd $0, t, t;
42 #define K(x0, x1, x2, x3, x4, i) \ argument
43 get_key(i, 0, x4); \
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
72 pslld $7, x3; \
74 por x4, x3; \
[all …]
/linux/arch/arm64/lib/
H A Dtishift.S12 mov x3, #64
13 sub x3, x3, x2
14 cmp x3, #0
17 lsr x3, x0, x3
19 orr x1, x1, x3
25 mov x2, #0
34 mov x3, #64
35 sub x3, x3, x2
36 cmp x3, #0
39 lsl x3, x1, x3
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_enum.h28 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
32 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
36 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
42 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
[all …]
H A Ddce_11_0_enum.h28 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
32 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
36 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
42 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-suniv-f1c100s.c32 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
36 SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
37 SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
38 SUNXI_FUNCTION(0x6, "spi1")), /* CS */
40 SUNXI_FUNCTION(0x0, "gpio_in"),
41 SUNXI_FUNCTION(0x1, "gpio_out"),
42 SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
[all …]
/linux/sound/soc/codecs/
H A Drk3308_codec.h12 #define RK3308_GLB_CON 0x00
17 * The ADC group are 0 ~ 3, that control:
24 #define RK3308_ADC_DIG_OFFSET(ch) (((ch) & 0x3) * 0xc0 + 0x0)
26 #define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x04)
27 #define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x08)
28 #define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x0c)
29 #define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x10)
30 #define RK3308_ADC_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x14) // ver.C only
31 #define RK3308_ADC_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x18) // ver.C only
32 #define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x1c)
[all …]
H A Drt1318.h36 #define RT1318_PLL_N_MAX 0x1ff
37 #define RT1318_PLL_K_MAX 0x1f
38 #define RT1318_PLL_M_MAX 0x1f
47 #define RT1318_CLK1 0xc001
48 #define RT1318_CLK2 0xc003
49 #define RT1318_CLK3 0xc004
50 #define RT1318_CLK4 0xc005
51 #define RT1318_CLK5 0xc006
52 #define RT1318_CLK6 0xc007
53 #define RT1318_CLK7 0xc008
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm-regbits-33xx.h13 #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
15 #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
17 #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
19 #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
21 #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
23 #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
30 #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
32 #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
33 #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
35 #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
[all …]

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