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/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccmreg.h32 #define CCM_CACCR 0x010
33 #define CCM_CBCDR 0x014
36 #define CCM_CSCMR1 0x01C
40 #define SSI_CLK_SEL_M 0x3
41 #define SSI_CLK_SEL_508_PFD 0
44 #define CCM_CSCMR2 0x020
46 #define CCM_CS1CDR 0x028
47 #define SSI1_CLK_PODF_SHIFT 0
51 #define SSI_CLK_PODF_MASK 0x3f
52 #define SSI_CLK_PRED_MASK 0x7
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-serdes.h13 #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
14 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
15 #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
16 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
18 #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
19 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
20 #define J721E_SERDES0_LANE1_USB3_0 0x2
21 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
23 #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
24 #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/mux/
H A Dti-serdes.h19 #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
20 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
21 #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
22 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
24 #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
25 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
26 #define J721E_SERDES0_LANE1_USB3_0 0x2
27 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_hsi_roce.h134 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
135 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
136 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
138 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
140 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
142 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
144 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
146 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
184 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
185 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
[all …]
H A Decore_hsi_rdma.h50 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */
51 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
52 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
54 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
56 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */
58 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */
61 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
62 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
[all …]
H A Decore_hsi_iscsi.h72 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
73 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
74 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */
76 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */
78 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
80 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
82 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */
84 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
86 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
89 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
[all …]
H A Decore_hsi_eth.h65 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
66 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
67 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
69 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
71 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
73 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
75 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
77 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
79 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
82 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
[all …]
H A Decore_hsi_fcoe.h60 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protec…
61 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
62 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (the…
64 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
68 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */;
70 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
71 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
72 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
74 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
85 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
[all …]
/freebsd/lib/libc/tests/net/getaddrinfo/data/
H A Dno_host_v4v6_prefer_v4.exp1 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
2 ai1: flags 0x2 family 28 socktype 2 protocol 17 addrlen 28 host ::1 serv http
3 ai2: flags 0x2 family 28 socktype 1 protocol 6 addrlen 28 host ::1 serv http
4 ai3: flags 0x2 family 28 socktype 5 protocol 132 addrlen 28 host ::1 serv http
5 ai4: flags 0x2 family 2 socktype 2 protocol 17 addrlen 16 host 127.0.0.1 serv http
6 ai5: flags 0x2 family 2 socktype 1 protocol 6 addrlen 16 host 127.0.0.1 serv http
7 ai6: flags 0x2 family 2 socktype 5 protocol 132 addrlen 16 host 127.0.0.1 serv http
9 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
10 ai1: flags 0x2 family 28 socktype 2 protocol 17 addrlen 28 host ::1 serv echo
11 ai2: flags 0x2 family 28 socktype 1 protocol 6 addrlen 28 host ::1 serv echo
[all …]
H A Dno_host_v4v6.exp1 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
2 ai1: flags 0x2 family 28 socktype 2 protocol 17 addrlen 28 host ::1 serv http
3 ai2: flags 0x2 family 28 socktype 1 protocol 6 addrlen 28 host ::1 serv http
4 ai3: flags 0x2 family 28 socktype 5 protocol 132 addrlen 28 host ::1 serv http
5 ai4: flags 0x2 family 2 socktype 2 protocol 17 addrlen 16 host 127.0.0.1 serv http
6 ai5: flags 0x2 family 2 socktype 1 protocol 6 addrlen 16 host 127.0.0.1 serv http
7 ai6: flags 0x2 family 2 socktype 5 protocol 132 addrlen 16 host 127.0.0.1 serv http
9 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
10 ai1: flags 0x2 family 28 socktype 2 protocol 17 addrlen 28 host ::1 serv echo
11 ai2: flags 0x2 family 28 socktype 1 protocol 6 addrlen 28 host ::1 serv echo
[all …]
H A Dno_host_v4_only.exp1 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
2 ai1: flags 0x2 family 28 socktype 2 protocol 17 addrlen 28 host ::1 serv http
3 ai2: flags 0x2 family 28 socktype 1 protocol 6 addrlen 28 host ::1 serv http
4 ai3: flags 0x2 family 28 socktype 5 protocol 132 addrlen 28 host ::1 serv http
5 ai4: flags 0x2 family 2 socktype 2 protocol 17 addrlen 16 host 127.0.0.1 serv http
6 ai5: flags 0x2 family 2 socktype 1 protocol 6 addrlen 16 host 127.0.0.1 serv http
7 ai6: flags 0x2 family 2 socktype 5 protocol 132 addrlen 16 host 127.0.0.1 serv http
9 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
10 ai1: flags 0x2 family 28 socktype 2 protocol 17 addrlen 28 host ::1 serv echo
11 ai2: flags 0x2 family 28 socktype 1 protocol 6 addrlen 28 host ::1 serv echo
[all …]
/freebsd/contrib/bearssl/src/symcipher/
H A Daes_x86ni_ctr.c64 for (u = 0; u <= num_rounds; u ++) { in br_aes_x86ni_ctr_run()
68 while (len > 0) { in br_aes_x86ni_ctr_run()
69 __m128i x0, x1, x2, x3; in br_aes_x86ni_ctr_run() local
71 x0 = _mm_insert_epi32(ivx, br_bswap32(cc + 0), 3); in br_aes_x86ni_ctr_run()
74 x3 = _mm_insert_epi32(ivx, br_bswap32(cc + 3), 3); in br_aes_x86ni_ctr_run()
75 x0 = _mm_xor_si128(x0, sk[0]); in br_aes_x86ni_ctr_run()
76 x1 = _mm_xor_si128(x1, sk[0]); in br_aes_x86ni_ctr_run()
77 x2 = _mm_xor_si128(x2, sk[0]); in br_aes_x86ni_ctr_run()
78 x3 = _mm_xor_si128(x3, sk[0]); in br_aes_x86ni_ctr_run()
82 x3 = _mm_aesenc_si128(x3, sk[1]); in br_aes_x86ni_ctr_run()
[all …]
H A Daes_x86ni_cbcdec.c62 for (u = 0; u <= num_rounds; u ++) { in br_aes_x86ni_cbcdec_run()
65 while (len > 0) { in br_aes_x86ni_cbcdec_run()
66 __m128i x0, x1, x2, x3, e0, e1, e2, e3; in br_aes_x86ni_cbcdec_run() local
68 x0 = _mm_loadu_si128((void *)(buf + 0)); in br_aes_x86ni_cbcdec_run()
72 x3 = _mm_loadu_si128((void *)(buf + 48)); in br_aes_x86ni_cbcdec_run()
74 x0 = _mm_loadu_si128((void *)(buf + 0)); in br_aes_x86ni_cbcdec_run()
80 x3 = x2; in br_aes_x86ni_cbcdec_run()
83 x3 = x1; in br_aes_x86ni_cbcdec_run()
88 x3 = x0; in br_aes_x86ni_cbcdec_run()
94 e3 = x3; in br_aes_x86ni_cbcdec_run()
[all …]
H A Daes_pwr8_ctrcbc.c49 * AES subkeys are in registers 0 to 10/12/14 (depending on keys size)
58 * AES subkeys are in registers 0 to 10/12/14 (depending on keys size)
103 vxor(x, x, 0) \
116 vxor(x, x, 0) \
131 vxor(x, x, 0) \
148 vxor(x, x, 0) \
149 vxor(y, y, 0) \
172 vxor(x, x, 0) \
173 vxor(y, y, 0) \
200 vxor(x, x, 0) \
[all …]
/freebsd/contrib/netbsd-tests/lib/libc/net/getaddrinfo/
H A Dno_host_v4v6.exp1 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
2 ai1: flags 0x2 family 24 socktype 2 protocol 17 addrlen 28 host ::1 serv http
3 ai2: flags 0x2 family 24 socktype 1 protocol 6 addrlen 28 host ::1 serv http
4 ai3: flags 0x2 family 2 socktype 2 protocol 17 addrlen 16 host 127.0.0.1 serv http
5 ai4: flags 0x2 family 2 socktype 1 protocol 6 addrlen 16 host 127.0.0.1 serv http
7 arg: flags 0x2 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
8 ai1: flags 0x2 family 24 socktype 2 protocol 17 addrlen 28 host ::1 serv echo
9 ai2: flags 0x2 family 24 socktype 1 protocol 6 addrlen 28 host ::1 serv echo
10 ai3: flags 0x2 family 2 socktype 2 protocol 17 addrlen 16 host 127.0.0.1 serv echo
11 ai4: flags 0x2 family 2 socktype 1 protocol 6 addrlen 16 host 127.0.0.1 serv echo
[all …]
/freebsd/lib/libc/aarch64/string/
H A Dtimingsafe_memcmp.S24 mov w0, #0 // empty buffer always matches
48 csetm w0, lo // w0 = w3 >= w4 ? 0 : -1
49 csinc w0, w0, wzr, ls // w0 = w3 <=> w4 ? 1 : 0 : -1
57 bfi x3, x5, #32, #32 // join words in little endian
59 rev x3, x3 // swap word order
61 cmp x3, x4
62 csetm w0, lo // x0 = x3 >= w4 ? 0 : -1
63 csinc w0, w0, wzr, ls // x0 = x3 <=> w4 ? 1 : 0 : -1
66 .L0916: ldr x3, [x0]
71 cmp x3, x4 // mismatch in first pair?
[all …]

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