Searched +full:0 +full:x2f100000 (Results 1 – 5 of 5) sorted by relevance
| /freebsd/sys/contrib/device-tree/src/arm64/arm/ |
| H A D | foundation-v8-gicv3.dtsi | 13 ranges = <0x0 0x0 0x2f000000 0x100000>;
15 reg = <0x0 0x2f000000 0x0 0x10000>,
16 <0x0 0x2f10000
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| H A D | fvp-base-revc.dts | 15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x000>;
52 i-cache-size = <0x8000>;
55 d-cache-size = <0x8000>;
63 reg = <0x0 0x100>;
65 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
76 reg = <0x0 0x200>;
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | arm,gic-v3.yaml | 33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
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| /freebsd/usr.sbin/bhyve/aarch64/ |
| H A D | bhyverun_machdep.c | 55 #define FDT_BASE 0x100000
59 #define UART_MMIO_BASE 0x10000
60 #define UART_MMIO_SIZE 0x1000
62 #define RTC_MMIO_BASE 0x11000
63 #define RTC_MMIO_SIZE 0x1000
66 #define GIC_DIST_BASE 0x2f000000
67 #define GIC_DIST_SIZE 0x10000
68 #define GIC_REDIST_BASE 0x2f100000
127 if (bhyve_topology_parse(optarg) != 0) { in bhyve_optparse()
155 if (bhyve_pincpu_parse(optarg) != 0) { in bhyve_optparse()
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| /freebsd/tools/test/iconv/ref/ |
| H A D | UTF-32BE-rev | 1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
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