Searched +full:0 +full:x2f000000 (Results 1 – 8 of 8) sorted by relevance
| /linux/arch/arm64/boot/dts/arm/ |
| H A D | foundation-v8-gicv3.dtsi | 13 ranges = <0x0 0x0 0x2f000000 0x100000>; 15 reg = <0x0 0x2f000000 0x0 0x10000>, 16 <0x0 0x2f100000 0x0 0x200000>, 17 <0x0 0x2c000000 0x0 0x2000>, 18 <0x0 0x2c010000 0x0 0x2000>, 19 <0x0 0x2c02f000 0x0 0x2000>; 26 reg = <0x20000 0x20000>;
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| H A D | fvp-base-revc.dts | 15 /memreserve/ 0x80000000 0x00010000; 45 #size-cells = <0>; 50 CPU_SLEEP_0: cpu-sleep-0 { 53 arm,psci-suspend-param = <0x0010000>; 60 CLUSTER_SLEEP_0: cluster-sleep-0 { 63 arm,psci-suspend-param = <0x1010000>; 71 cpu0: cpu@0 { 74 reg = <0x0 0x000>; 76 i-cache-size = <0x8000>; 79 d-cache-size = <0x8000>; [all …]
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,gic-v5-iwb.yaml | 35 const: 0 42 bits[3:0] trigger type and level flags. 69 reg = <0x2f000000 0x10000>; 71 #address-cells = <0>;
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| H A D | arm,gic-v3.yaml | 33 enum: [ 0, 1, 2 ] 46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 51 SPI interrupts are in the range [0-987]. PPI interrupts are in the 52 range [0-15]. Extended SPI interrupts are in the range [0-1023]. 53 Extended PPI interrupts are in the range [0-127]. 56 bits[3:0] trigger type and level flags. 68 of 0 if present. 83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and 99 multipleOf: 0x10000 100 exclusiveMinimum: 0 [all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| H A D | nbio_7_0_default.h | 26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000 27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000 28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000 29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000 30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000 31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000 32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000 33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000 34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000 35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000 [all …]
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| H A D | nbio_2_3_default.h | 26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000 27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000 28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000 32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 34 #define mmPCIE_INDEX_DEFAULT 0x00000000 35 #define mmPCIE_DATA_DEFAULT 0x00000000 36 #define mmPCIE_INDEX2_DEFAULT 0x00000000 37 #define mmPCIE_DATA2_DEFAULT 0x00000000 38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 [all …]
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| H A D | nbio_6_1_default.h | 26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000 27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000 28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000 29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000 30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000 31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000 32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000 33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000 34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000 35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000 [all …]
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| /linux/arch/hexagon/kernel/ |
| H A D | vm_init_segtable.S | 16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages. 46 /* VA 0x00000000 */ 59 /* VA 0x40000000 */ 68 /* VA 0x80000000 */ 74 /*0xa8*/.word X,X,X,X 77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000) 79 /*0xa9*/.word X,X,X,X 81 /*0xaa*/.word X,X,X,X 82 /*0xab*/.word X,X,X,X 83 /*0xac*/.word X,X,X,X [all …]
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