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/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-sbc-t3730.dts21 pinctrl-0 = <&sb_t35_usb_hub_pins>;
25 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
31 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
32 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
33 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
H A Domap3-sbc-t3530.dts21 pinctrl-0 = <&sb_t35_usb_hub_pins>;
25 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
31 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
32 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
33 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
37 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-vpu.dtsi10 ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
11 reg = <0 0x2c000000 0 0x1000000>;
17 reg = <0x2d000000 0x20000>;
26 reg = <0x2d020000 0x20000>;
35 reg = <0x2d040000 0x20000>;
43 reg = <0x2d080000 0x10000>;
47 mboxes = <&mu_m0 0 0>,
48 <&mu_m0 0 1>,
49 <&mu_m0 1 0>;
54 reg = <0x2d090000 0x10000>;
[all …]
H A Dimx8ulp.dtsi37 #size-cells = <0>;
39 A35_0: cpu@0 {
42 reg = <0x0 0x0>;
51 reg = <0x0 0x1>;
68 arm,psci-suspend-param = <0x0>;
79 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
80 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
103 thermal-sensors = <&scmi_sensor 0>;
133 #clock-cells = <0>;
140 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
15 ranges = <0 0x0 0x2a820000 0x20000>;
20 reg = <0x10000 0x10000>;
26 reg = <0x0 0x2b1f0000 0x0 0x1000>;
37 reg = <0x0 0x2b400000 0x0 0x10000>;
49 reg = <0x0 0x2b500000 0x0 0x10000>;
60 reg = <0x0 0x2b600000 0x0 0x10000>;
66 power-domains = <&scpi_devpd 0>;
71 reg = <0x0 0x2c010000 0 0x1000>,
72 <0x0 0x2c02f000 0 0x2000>,
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
H A Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
[all …]
H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]