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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-vpu.dtsi10 ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
11 reg = <0 0x2c000000 0 0x1000000>;
17 reg = <0x2d000000 0x20000>;
26 reg = <0x2d020000 0x20000>;
35 reg = <0x2d040000 0x20000>;
43 reg = <0x2d080000 0x10000>;
47 mboxes = <&mu_m0 0 0>,
48 <&mu_m0 0 1>,
49 <&mu_m0 1 0>;
54 reg = <0x2d090000 0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Damphion,vpu.yaml20 pattern: "^vpu@[0-9a-f]+$"
43 "^mailbox@[0-9a-f]+$":
50 "^vpu-core@[0-9a-f]+$":
116 ranges = <0x2c000000 0x2c000000 0x2000000>;
117 reg = <0x2c000000 0x1000000>;
124 reg = <0x2d000000 0x20000>;
125 interrupts = <0 472 4>;
132 reg = <0x2d020000 0x20000>;
133 interrupts = <0 473 4>;
140 reg = <0x2d040000 0x20000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8-gicv3.dtsi13 ranges = <0x0 0x0 0x2f000000 0x100000>;
15 reg = <0x0 0x2f000000 0x0 0x10000>,
16 <0x0 0x2f10000
[all...]
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x000>;
52 i-cache-size = <0x8000>;
55 d-cache-size = <0x8000>;
63 reg = <0x0 0x100>;
65 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
76 reg = <0x0 0x200>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3-sbc-t3730.dts21 pinctrl-0 = <&sb_t35_usb_hub_pins>;
25 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
31 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
32 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
33 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
H A Domap3-sbc-t3530.dts21 pinctrl-0 = <&sb_t35_usb_hub_pins>;
25 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
31 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
32 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
33 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
37 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
H A Domap3-cm-t3x30.dtsi10 cpu@0 {
27 OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */
28 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */
34 OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
35 OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
36 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
37 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
38 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
39 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
40 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
[all …]
H A Domap-zoom-common.dtsi9 ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */
10 <7 0 0x2c000000 0x01000000>;
17 serial@3,0 {
19 reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
27 gpmc,mux-add-data = <0>;
48 gpmc,wait-monitoring-ns = <0>;
49 gpmc,clk-activation-ns = <0>;
55 reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */
66 reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */
77 reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */
[all …]
H A Domap4-duovero-parlor.dts31 #size-cells = <0>;
59 pinctrl-0 = <
67 OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */
73 OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */
79 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
80 OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
86 OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
87 OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
93 OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */
94 OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */
[all …]
H A Domap3-evm-processor-common.dtsi8 reg = <0x80000000 0x10000000>; /* 256 MB */
13 pinctrl-0 = <&wl12xx_gpio>;
21 pinctrl-0 = <
29 pinctrl-0 = <&ehci_phy_pins>;
34 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>;
38 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
39 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
40 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
41 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
43 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
[all …]
H A Dlogicpd-som-lv-baseboard.dtsi7 pinctrl-0 = <&gpio_key_pins>;
26 pinctrl-0 = <&led_pins &led_pins_wkup>;
55 pinctrl-0 = <&mcbsp2_pins>;
64 ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
65 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */
66 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */
70 pinctrl-0 = <&lan9221_pins>;
73 reg = <1 0 0xff>;
86 pinctrl-0 = <&dss_dpi_pins1>;
111 pinctrl-0 = <&lcd_enable_pin>;
[all …]
H A Domap3-igep0020-common.dtsi16 pinctrl-0 = <&leds_pins>;
58 #phy-cells = <0>;
67 #size-cells = <0>;
69 port@0 {
70 reg = <0>;
105 pinctrl-0 = <
112 OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
118 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
119 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
120 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
[all …]
H A Domap3-overo-base.dtsi12 memory@0 {
14 reg = <0 0>;
51 #phy-cells = <0>;
67 pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
79 pinctrl-0 = <
85 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
86 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
87 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
88 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
94 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
[all …]
H A Domap3-devkit8000-common.dtsi12 reg = <0x80000000 0x10000000>; /* 256 MB */
74 #size-cells = <0>;
76 port@0 {
77 reg = <0>;
125 reg = <0x48>;
165 timer@0 {
174 timer@0 {
186 ti,pulldowns = <0x03a1c6>;
190 linux,keymap = <MATRIX_KEY(0,
[all...]
H A Dlogicpd-torpedo-baseboard.dtsi7 pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>;
47 pinctrl-0 = <&led_pins>;
65 pinctrl-0 = <&pwm_pins>;
68 ti,clock-source = <0x01>;
85 pinctrl-0 = <&mcbsp2_pins>;
95 ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
96 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */
97 6 0 0x28000000 0x1000000>; /* CS6: 16MB for ISP1763 */
101 pinctrl-0 = <&lan9221_pins>;
104 reg = <1 0 0xff>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dgpmc-eth.txt41 Note that base address will be typically 0 as this
53 reg = <0x6e000000 0x1000>;
60 ranges = <5 0 0x2c000000 0x1000000>;
62 ethernet@5,0 {
64 reg = <5 0 0xff>;
68 gpmc,cs-on-ns = <0>;
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca5s.dts16 arm,hbi = <0x225>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
55 reg = <0x80000000 0x40000000>;
63 /* Chipselect 2 is physically at 0x18000000 */
67 reg = <0x18000000 0x00800000>;
74 reg = <0x2a110000 0x1000>;
75 interrupts = <0 85 4>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/dev/rl/
H A Dif_rlreg.h36 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
38 #define RL_IDR2 0x0002
39 #define RL_IDR3 0x0003
40 #define RL_IDR4 0x0004
41 #define RL_IDR5 0x0005
43 #define RL_MAR0 0x0008 /* Multicast hash table */
44 #define RL_MAR1 0x0009
45 #define RL_MAR2 0x000A
46 #define RL_MAR3 0x000B
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
/freebsd/sys/powerpc/powerpc/
H A Ddb_disasm.c17 Op_A = 0x00000001,
18 Op_B = 0x00000002,
19 Op_BI = 0x00000004,
20 Op_BO = 0x00000008,
22 Op_CRM = 0x00000010,
23 Op_D = 0x00000020,
24 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */
25 Op_S = 0x00000040, /* S-field is swapped with A-field */
27 Op_dA = 0x00000080,
28 Op_LK = 0x00000100,
[all …]
/freebsd/tests/sys/cddl/zfs/tests/txg_integrity/
H A Dtxg_integrity.c84 #define USE_MMAP 0
90 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
94 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
98 //chunk 0 corresponds to bit 1, chunk 1 to bit 2, etc
106 if (chunk == 0){ in get_chunk_range()
107 *begin = 0; in get_chunk_range()
117 leader_syncs = 0,
125 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
126 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
127 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
[all …]
H A Dfsync_integrity.c61 * Every even-numbered thread, starting with the first (0th), will fsync()
98 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
102 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
116 if (chunk == 0){ in get_chunk_range()
117 *begin = 0; in get_chunk_range()
129 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
130 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
131 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
132 0x32000000, 0x34000000, 0x36000000, 0x38000000, 0x3a000000, 0x3c000000, 0x3e000000, 0x40000000,
133 0x42000000, 0x44000000, 0x46000000, 0x48000000, 0x4a000000, 0x4c000000, 0x4e000000, 0x50000000,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
13 def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
15 SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
16 def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
18 def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>,
20 SDTCisSameAs<0, 2>,
22 def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,
23 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
24 def SDT_loongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>,
25 SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
[all …]

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