Searched +full:0 +full:x2990000 (Results 1 – 4 of 4) sorted by relevance
152 * from 0x40000000 - 0x5fffffff. Anything outside is reserved by155 iommu-addresses = <&adsp 0x0 0x00000000 0x00 0x40000000>,156 <&adsp 0x0 0x60000000 0xff 0xa0000000>;160 reg = <0x0 0x90000000 0x0 0x00800000>;161 iommu-addresses = <&dc0 0x0 0x90000000 0x0 0x00800000>;165 bus@0 {168 ranges = <0x0 0x0 0x0 0x40000000>;171 reg = <0x2990000 0x2000>;176 reg = <0x15200000 0x10000>;
37 #size-cells = <0>;45 cpu0: cpu@0 {48 reg = <0x0>;49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;58 reg = <0x1>;59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;68 reg = <0x2>;69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;78 reg = <0x3>;79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;[all …]
38 #size-cells = <0>;40 cpu0: cpu@0 {43 reg = <0x0>;44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;53 reg = <0x1>;54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;63 reg = <0x2>;64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;73 reg = <0x3>;74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;[all …]
31 #size-cells = <0>;36 reg = <0xf00>;37 clocks = <&clockgen 1 0>;44 reg = <0xf01>;45 clocks = <&clockgen 1 0>;50 memory@0 {52 reg = <0x0 0x0 0x0 0x0>;57 #clock-cells = <0>;80 offset = <0xb0>;81 mask = <0x02>;[all …]