Searched +full:0 +full:x256 (Results 1 – 14 of 14) sorted by relevance
| /linux/arch/arc/include/asm/ |
| H A D | perf_event.h | 15 #define ARC_REG_CC_BUILD 0xF6 16 #define ARC_REG_CC_INDEX 0x240 17 #define ARC_REG_CC_NAME0 0x241 18 #define ARC_REG_CC_NAME1 0x242 20 #define ARC_REG_PCT_BUILD 0xF5 21 #define ARC_REG_PCT_COUNTL 0x250 22 #define ARC_REG_PCT_COUNTH 0x251 23 #define ARC_REG_PCT_SNAPL 0x252 24 #define ARC_REG_PCT_SNAPH 0x253 25 #define ARC_REG_PCT_CONFIG 0x254 [all …]
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| /linux/drivers/video/fbdev/ |
| H A D | acornfb.c | 64 .hfmin = 0, 66 .vfmin = 0, 120 memset(&vidc, 0, sizeof(vidc)); in acornfb_set_timing() 162 vidc_writel(0xd0000000 | vidc.pll_ctl); in acornfb_set_timing() 163 vidc_writel(0x80000000 | vidc.h_cycle); in acornfb_set_timing() 164 vidc_writel(0x81000000 | vidc.h_sync_width); in acornfb_set_timing() 165 vidc_writel(0x82000000 | vidc.h_border_start); in acornfb_set_timing() 166 vidc_writel(0x83000000 | vidc.h_display_start); in acornfb_set_timing() 167 vidc_writel(0x84000000 | vidc.h_display_end); in acornfb_set_timing() 168 vidc_writel(0x85000000 | vidc.h_border_end); in acornfb_set_timing() [all …]
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| H A D | arcfb.c | 14 * can be paneled in a variety of setups such as 2x1=128x64, 4x4=256x256 and 32 * - User must set dio_addr=0xIOADDR cio_addr=0xIOADDR 52 #define floor8(a) (a&(~0x07)) 55 #define ceil64(a) (a|0x3F) 60 #define KS_SET_DPY_START_LINE 0xC0 61 #define KS_SET_PAGE_NUM 0xB8 62 #define KS_SET_X 0x40 63 #define KS_CEHI 0x01 64 #define KS_CELO 0x00 65 #define KS_SEL_CMD 0x08 [all …]
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| H A D | amifb.c | 71 # define IS_OCS (0) 80 # define IS_ECS (0) 89 # define IS_AGA (0) 171 (0, 0) is somewhere in the upper-left corner :-) 203 (0, 0) is somewhere in the upper-left corner :-) 258 < 192 -> sprite 0 dma 373 #define CUSTOM_OFS(fld) ((long)&((struct CUSTOM*)0)->fld) 376 * BPLCON0 -- Bitplane Control Register 0 379 #define BPC0_HIRES (0x8000) 380 #define BPC0_BPU2 (0x4000) /* Bit plane used count */ [all …]
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| /linux/drivers/crypto/inside-secure/ |
| H A D | safexcel.h | 20 #define EIP197_HIA_VERSION_BE 0xca35 21 #define EIP197_HIA_VERSION_LE 0x35ca 22 #define EIP97_VERSION_LE 0x9e61 23 #define EIP196_VERSION_LE 0x3bc4 24 #define EIP197_VERSION_LE 0x3ac5 25 #define EIP96_VERSION_LE 0x9f60 26 #define EIP201_VERSION_LE 0x36c9 27 #define EIP206_VERSION_LE 0x31ce 28 #define EIP207_VERSION_LE 0x30cf 29 #define EIP197_REG_LO16(reg) (reg & 0xffff) [all …]
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu7_ppsmc.h | 30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305) 32 #define PPSMC_SWSTATE_FLAG_DC 0x01 33 #define PPSMC_SWSTATE_FLAG_UVD 0x02 34 #define PPSMC_SWSTATE_FLAG_VCE 0x04 36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04 [all …]
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| H A D | tonga_ppsmc.h | 29 #define PPSMC_SWSTATE_FLAG_DC 0x01 30 #define PPSMC_SWSTATE_FLAG_UVD 0x02 31 #define PPSMC_SWSTATE_FLAG_VCE 0x04 32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04 [all …]
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| H A D | fiji_ppsmc.h | 30 #define PPSMC_SWSTATE_FLAG_DC 0x01 31 #define PPSMC_SWSTATE_FLAG_UVD 0x02 32 #define PPSMC_SWSTATE_FLAG_VCE 0x04 34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04 42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 [all …]
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| /linux/Documentation/arch/m68k/ |
| H A D | kernel-options.rst | 13 0) Introduction 76 /dev/ram: -> 0x0100 (initial ramdisk) 77 /dev/hda: -> 0x0300 (first IDE disk) 78 /dev/hdb: -> 0x0340 (second IDE disk) 79 /dev/sda: -> 0x0800 (first SCSI disk) 80 /dev/sdb: -> 0x0810 (second SCSI disk) 81 /dev/sdc: -> 0x0820 (third SCSI disk) 82 /dev/sdd: -> 0x0830 (forth SCSI disk) 83 /dev/sde: -> 0x0840 (fifth SCSI disk) 84 /dev/fd : -> 0x0200 (floppy disk) [all …]
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| /linux/drivers/media/i2c/ |
| H A D | max96717.c | 23 #define MAX96717_DEVICE_ID 0xbf 24 #define MAX96717F_DEVICE_ID 0xc8 26 #define MAX96717_PAD_SINK 0 33 #define MAX96717_REG3 CCI_REG8(0x3) 34 #define MAX96717_RCLKSEL GENMASK(1, 0) 35 #define RCLKSEL_REF_PLL CCI_REG8(0x3) 36 #define MAX96717_REG6 CCI_REG8(0x6) 38 #define MAX96717_DEV_ID CCI_REG8(0xd) 39 #define MAX96717_DEV_REV CCI_REG8(0xe) 40 #define MAX96717_DEV_REV_MASK GENMASK(3, 0) [all …]
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| /linux/drivers/media/usb/gspca/ |
| H A D | spca508.c | 23 #define CreativeVista 0 51 .priv = 0}, 62 {0x0000, 0x870b}, 64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */ 65 {0x0003, 0x8111}, /* Reset compression & memory */ 66 {0x0000, 0x8110}, /* Disable all outputs */ 67 /* READ {0x0000, 0x8114} -> 0000: 00 */ 68 {0x0000, 0x8114}, /* SW GPIO data */ 69 {0x0008, 0x8110}, /* Enable charge pump output */ 70 {0x0002, 0x8116}, /* 200 kHz pump clock */ [all …]
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| /linux/sound/drivers/opl4/ |
| H A D | opl4_synth.c | 41 #define MIDI_CTL_RELEASE_TIME 0x48 42 #define MIDI_CTL_ATTACK_TIME 0x49 43 #define MIDI_CTL_DECAY_TIME 0x4b 44 #define MIDI_CTL_VIBRATO_RATE 0x4c 45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d 46 #define MIDI_CTL_VIBRATO_DELAY 0x4e 52 static const s16 snd_opl4_pitch_map[0x600] = { 53 0x000,0x000,0x00 [all...] |
| /linux/drivers/net/wireless/broadcom/b43/ |
| H A D | phy_n.h | 11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */ 12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */ 13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */ 14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */ 15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */ 16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */ 17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ 18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */ 19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */ 20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */ [all …]
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| /linux/drivers/gpu/drm/msm/registers/adreno/ |
| H A D | a5xx.xml | 10 <value value="0x02" name="RB5_A8_UNORM"/> 11 <value value="0x03" name="RB5_R8_UNORM"/> 12 <value value="0x04" name="RB5_R8_SNORM"/> 13 <value value="0x05" name="RB5_R8_UINT"/> 14 <value value="0x06" name="RB5_R8_SINT"/> 15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/> 16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/> 17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/> 18 <value value="0x0f" name="RB5_R8G8_UNORM"/> 19 <value value="0x10" name="RB5_R8G8_SNORM"/> [all …]
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