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/linux/arch/arc/include/asm/
H A Dperf_event.h15 #define ARC_REG_CC_BUILD 0xF6
16 #define ARC_REG_CC_INDEX 0x240
17 #define ARC_REG_CC_NAME0 0x241
18 #define ARC_REG_CC_NAME1 0x242
20 #define ARC_REG_PCT_BUILD 0xF5
21 #define ARC_REG_PCT_COUNTL 0x250
22 #define ARC_REG_PCT_COUNTH 0x251
23 #define ARC_REG_PCT_SNAPL 0x252
24 #define ARC_REG_PCT_SNAPH 0x253
25 #define ARC_REG_PCT_CONFIG 0x254
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/linux/drivers/gpu/drm/ci/xfails/
H A Dvkms-none-fails.txt17 kms_content_protection@lic-type-0,Crash
24 kms_cursor_crc@cursor-rapid-movement-256x256,Fail
H A Dvkms-none-skips.txt7 # CPU: 0 PID: 2635 Comm: kworker/u8:13 Not tainted 6.9.0-rc7-g40935263a1fd #1
8 # Hardware name: ChromiumOS crosvm, BIOS 0
10 # RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms]
11 …c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b…
23 # ? __die+0x1e/0x60
24 # ? page_fault_oops+0x17b/0x490
25 # ? exc_page_fault+0x6d/0x230
26 # ? asm_exc_page_fault+0x26/0x30
27 # ? compose_active_planes+0x1c7/0x4e0 [vkms]
28 # ? compose_active_planes+0x2a3/0x4e0 [vkms]
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/linux/Documentation/devicetree/bindings/sound/
H A Drenesas,rz-ssi.yaml65 bits[0:9] - Specifies MID/RID value of a SSI channel as below
66 MID/RID value of SSI rx0 = 0x256
67 MID/RID value of SSI tx0 = 0x255
68 MID/RID value of SSI rx1 = 0x25a
69 MID/RID value of SSI tx1 = 0x259
70 MID/RID value of SSI rt2 = 0x25f
71 MID/RID value of SSI rx3 = 0x262
72 MID/RID value of SSI tx3 = 0x261
75 bit[11] - LVL = 0, Detects based on the edge
77 bit[15] - TM = 0, Single transfer mode
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/linux/drivers/video/fbdev/
H A Dacornfb.c64 .hfmin = 0,
66 .vfmin = 0,
120 memset(&vidc, 0, sizeof(vidc)); in acornfb_set_timing()
162 vidc_writel(0xd0000000 | vidc.pll_ctl); in acornfb_set_timing()
163 vidc_writel(0x80000000 | vidc.h_cycle); in acornfb_set_timing()
164 vidc_writel(0x81000000 | vidc.h_sync_width); in acornfb_set_timing()
165 vidc_writel(0x82000000 | vidc.h_border_start); in acornfb_set_timing()
166 vidc_writel(0x83000000 | vidc.h_display_start); in acornfb_set_timing()
167 vidc_writel(0x84000000 | vidc.h_display_end); in acornfb_set_timing()
168 vidc_writel(0x85000000 | vidc.h_border_end); in acornfb_set_timing()
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H A Darcfb.c14 * can be paneled in a variety of setups such as 2x1=128x64, 4x4=256x256 and
32 * - User must set dio_addr=0xIOADDR cio_addr=0xIOADDR
52 #define floor8(a) (a&(~0x07))
55 #define ceil64(a) (a|0x3F)
60 #define KS_SET_DPY_START_LINE 0xC0
61 #define KS_SET_PAGE_NUM 0xB8
62 #define KS_SET_X 0x40
63 #define KS_CEHI 0x01
64 #define KS_CELO 0x00
65 #define KS_SEL_CMD 0x08
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H A Damifb.c71 # define IS_OCS (0)
80 # define IS_ECS (0)
89 # define IS_AGA (0)
171 (0, 0) is somewhere in the upper-left corner :-)
203 (0, 0) is somewhere in the upper-left corner :-)
258 < 192 -> sprite 0 dma
373 #define CUSTOM_OFS(fld) ((long)&((struct CUSTOM*)0)->fld)
376 * BPLCON0 -- Bitplane Control Register 0
379 #define BPC0_HIRES (0x8000)
380 #define BPC0_BPU2 (0x4000) /* Bit plane used count */
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/linux/drivers/crypto/inside-secure/
H A Dsafexcel.h20 #define EIP197_HIA_VERSION_BE 0xca35
21 #define EIP197_HIA_VERSION_LE 0x35ca
22 #define EIP97_VERSION_LE 0x9e61
23 #define EIP196_VERSION_LE 0x3bc4
24 #define EIP197_VERSION_LE 0x3ac5
25 #define EIP96_VERSION_LE 0x9f60
26 #define EIP201_VERSION_LE 0x36c9
27 #define EIP206_VERSION_LE 0x31ce
28 #define EIP207_VERSION_LE 0x30cf
29 #define EIP197_REG_LO16(reg) (reg & 0xffff)
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/linux/Documentation/arch/m68k/
H A Dkernel-options.rst13 0) Introduction
76 /dev/ram: -> 0x0100 (initial ramdisk)
77 /dev/hda: -> 0x0300 (first IDE disk)
78 /dev/hdb: -> 0x0340 (second IDE disk)
79 /dev/sda: -> 0x0800 (first SCSI disk)
80 /dev/sdb: -> 0x0810 (second SCSI disk)
81 /dev/sdc: -> 0x0820 (third SCSI disk)
82 /dev/sdd: -> 0x0830 (forth SCSI disk)
83 /dev/sde: -> 0x0840 (fifth SCSI disk)
84 /dev/fd : -> 0x0200 (floppy disk)
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/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
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H A Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
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H A Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
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/linux/drivers/gpu/drm/i915/gvt/
H A Dfb_decoder.c51 int bpp; /* Bits per pixel, 0 indicates invalid */
64 /* non-supported format has bpp default to 0 */
84 /* non-supported format has bpp default to 0 */
94 bdw_pixel_formats_index = 0; in bdw_format_to_drm()
193 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()
207 * 0 on success, non-zero if failed.
248 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); in intel_vgpu_decode_primary_plane()
260 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_primary_plane()
283 return 0; in intel_vgpu_decode_primary_plane()
289 u8 bpp; /* Bits per pixel; 0 indicates invalid */
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/linux/drivers/media/i2c/
H A Dmax96717.c23 #define MAX96717_DEVICE_ID 0xbf
24 #define MAX96717F_DEVICE_ID 0xc8
26 #define MAX96717_PAD_SINK 0
33 #define MAX96717_REG3 CCI_REG8(0x3)
34 #define MAX96717_RCLKSEL GENMASK(1, 0)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
40 #define MAX96717_DEV_REV_MASK GENMASK(3, 0)
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/linux/drivers/media/usb/gspca/
H A Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
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/linux/sound/drivers/opl4/
H A Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
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/linux/include/drm/display/
H A Ddrm_dp.h44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Ddisp.c87 if (ret < 0) in nv50_chan_create()
90 while (oclass[0]) { in nv50_chan_create()
91 for (i = 0; i < n; i++) { in nv50_chan_create()
92 if (sclass[i].oclass == oclass[0]) { in nv50_chan_create()
93 ret = nvif_object_ctor(disp, "kmsChan", 0, in nv50_chan_create()
94 oclass[0], data, size, in nv50_chan_create()
96 if (ret == 0) { in nv50_chan_create()
97 ret = nvif_object_map(&chan->user, NULL, 0); in nv50_chan_create()
145 nvif_wr32(&device->object, 0x070000, 0x00000001); in nv50_dmac_kick()
147 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) in nv50_dmac_kick()
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/linux/drivers/hid/bpf/progs/
H A Dhid_report_helpers.h22 * returns 0, which allows using it everywhere an expression
27 0 * (int) sizeof( \
36 #define i4(v_) (((__u8)(v_) & 0xf) + must_be((v_) >= -0x8 && (v_) <= 0x7, "not a i4"))
37 #define i8(v_) ((__u8)(v_) + must_be((v_) >= -0x80 && (v_) <= 0xff, "not a i8/u8"))
38 #define i16(v_) ((__u16)(v_) + must_be((v_) >= -0x8000 && (v_) <= 0xffff, "not a i16/u16"))
39 #define i32(v_) ((__u32)(v_) + must_be((v_) >= -0x80000000L && (v_) <= 0xffffffffL, \
43 #define LE16(v_) i16(v_) & 0xff, ((v_) >> 8) & 0xff
44 #define LE32(v_) i32(v_) & 0xff, ((v_) >> 8) & 0xff, ((v_) >> 16) & 0xff, ((v_) >> 24) & 0xff
47 * of the collection (0xa?) and the EndCollection item (0xc?).
55 * LogicalRange_i8(0, 1)
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da5xx.xml10 <value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
19 <value value="0x10" name="RB5_R8G8_SNORM"/>
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