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/linux/Documentation/devicetree/bindings/i2c/
H A Dhpe,gxp-i2c.yaml48 reg = <0x2500 0x70>;
51 #size-cells = <0>;
57 reg = <0x50>;
/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,armada-370-neta.yaml70 reg = <0x70000 0x2500>;
77 bm,pool-long = <0>;
/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
H A Da3xx_gpu.c36 for (i = 0; i < submit->nr_cmds; i++) { in a3xx_submit()
67 OUT_RING(ring, 0x00000000); in a3xx_submit()
75 #if 0 in a3xx_submit()
79 OUT_RING(ring, 0x00000000); in a3xx_submit()
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
90 OUT_RING(ring, 0x000003f7); in a3xx_me_init()
91 OUT_RING(ring, 0x00000000); in a3xx_me_init()
92 OUT_RING(ring, 0x00000000); in a3xx_me_init()
93 OUT_RING(ring, 0x00000000); in a3xx_me_init()
94 OUT_RING(ring, 0x00000080); in a3xx_me_init()
[all …]
/linux/drivers/regulator/
H A Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dqcom,ufs.yaml191 reg = <0x0 0x01d84000 0x0 0x2500>,
192 <0x0 0x01d90000 0x0 0x8000>;
210 iommus = <&apps_smmu 0x300 0>;
231 <0 0>,
232 <0 0>,
234 <0 0>,
235 <0 0>,
236 <0 0>,
237 <0 0>,
238 <0 300000000>;
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux/drivers/net/ethernet/realtek/rtase/
H A Drtase.h12 #define RTASE_HW_VER_MASK 0x7C800000
13 #define RTASE_HW_VER_906X_7XA 0x00800000
14 #define RTASE_HW_VER_906X_7XC 0x04000000
15 #define RTASE_HW_VER_907XD_V1 0x04800000
16 #define RTASE_HW_VER_907XD_VA 0x08000000
26 #define RTASE_INTERFRAMEGAP 0x03
29 #define RTASE_PCI_REGS_SIZE 0x100
42 #define RTASE_MITI_TIME_COUNT_MASK GENMASK(3, 0)
60 RTASE_MAC0 = 0x0000,
61 RTASE_MAC4 = 0x0004,
[all …]
/linux/drivers/media/usb/hdpvr/
H A Dhdpvr.h22 #define HD_PVR_VENDOR_ID 0x2040
23 #define HD_PVR_PRODUCT_ID 0x4900
24 #define HD_PVR_PRODUCT_ID1 0x4901
25 #define HD_PVR_PRODUCT_ID2 0x4902
26 #define HD_PVR_PRODUCT_ID4 0x4903
27 #define HD_PVR_PRODUCT_ID3 0x4982
33 #define HDPVR_FIRMWARE_VERSION 0x08
34 #define HDPVR_FIRMWARE_VERSION_AC3 0x0d
35 #define HDPVR_FIRMWARE_VERSION_0X12 0x12
36 #define HDPVR_FIRMWARE_VERSION_0X15 0x15
[all …]
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux/drivers/comedi/drivers/
H A Dni_atmio.c87 RANGE_ext(0, 1)
96 .isapnp_id = 0x0000, /* XXX unknown */
98 .ai_maxdata = 0x0fff,
103 .ao_maxdata = 0x0fff,
111 .isapnp_id = 0x1900,
113 .ai_maxdata = 0x0fff,
118 .ao_maxdata = 0x0fff,
126 .isapnp_id = 0x2400,
128 .ai_maxdata = 0x0fff,
133 .ao_maxdata = 0x0fff,
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc.h46 #define PWC_DEBUG_LEVEL_MODULE BIT(0)
74 } while (0)
86 #define PWC_TRACE(fmt, args...) do { } while(0)
87 #define PWC_DEBUG(level, fmt, args...) do { } while(0)
89 #define pwc_trace 0
97 #define FEATURE_MOTOR_PANTILT 0x0001
98 #define FEATURE_CODEC1 0x0002
99 #define FEATURE_CODEC2 0x0004
127 #define SET_LUM_CTL 0x01
128 #define GET_LUM_CTL 0x02
[all …]
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7757.c33 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
34 DEFINE_RES_IRQ(evt2irq(0x700)),
39 .id = 0,
53 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
54 DEFINE_RES_IRQ(evt2irq(0xb80)),
73 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
74 DEFINE_RES_IRQ(evt2irq(0xf00)),
92 DEFINE_RES_MEM(0xfe430000, 0x20),
93 DEFINE_RES_IRQ(evt2irq(0x580)),
94 DEFINE_RES_IRQ(evt2irq(0x5a0)),
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x008
[all...]
/linux/lib/
H A Dtest_maple_tree.c14 #define MTREE_ALLOC_MAX 0x2000000000000Ul
19 #define mt_dump(mt, fmt) do {} while (0)
20 #define mt_validate(mt) do {} while (0)
21 #define mt_cache_shrink() do {} while (0)
22 #define mas_dump(mas) do {} while (0)
23 #define mas_wr_dump(mas) do {} while (0)
39 } while (0)
53 #define mt_set_non_kernel(x) do {} while (0)
54 #define mt_zero_nr_tallocated(x) do {} while (0)
56 #define cond_resched() do {} while (0)
[all …]
/linux/include/sound/
H A Dcs42l42.h15 #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
16 #define CS42L42_WIN_START 0x00
17 #define CS42L42_WIN_LEN 0x100
18 #define CS42L42_RANGE_MIN 0x00
19 #define CS42L42_RANGE_MAX 0x7F
21 #define CS42L42_PAGE_10 0x1000
22 #define CS42L42_PAGE_11 0x1100
23 #define CS42L42_PAGE_12 0x1200
24 #define CS42L42_PAGE_13 0x1300
25 #define CS42L42_PAGE_15 0x1500
[all …]
/linux/drivers/usb/core/
H A Dquirks.c49 quirk_count = 0; in quirks_param_set()
55 for (quirk_count = 1, i = 0; val[i]; i++) in quirks_param_set()
67 quirk_count = 0; in quirks_param_set()
73 for (i = 0, p = val; p && *p;) { in quirks_param_set()
94 for (flags = 0; *field; field++) { in quirks_param_set()
159 return 0; in quirks_param_set()
194 { USB_DEVICE(0x0204, 0x6025), .driver_info = USB_QUIRK_RESET_RESUME },
197 { USB_DEVICE(0x0218, 0x0201), .driver_info =
201 { USB_DEVICE(0x0218, 0x0401), .driver_info =
205 { USB_DEVICE(0x03f0, 0x0701), .driver_info =
[all …]
/linux/fs/nls/
H A Dnls_cp857.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
H A Dnls_cp866.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
H A Dnls_cp855.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]

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