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/linux/drivers/clk/hisilicon/
H A Dclk-hi6220.c23 { HI6220_REF32K, "ref32k", NULL, 0, 32764, },
24 { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, },
25 { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, },
26 { HI6220_MMC2_PAD, "mmc2_pad", NULL, 0, 100000000, },
27 { HI6220_MMC0_PAD, "mmc0_pad", NULL, 0, 200000000, },
28 { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, },
29 { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,},
30 { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,},
31 { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,},
32 { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,},
[all …]
/linux/drivers/memory/tegra/
H A Dtegra124.c16 .id = 0x00,
21 .reg = 0x34c,
22 .shift = 0,
23 .mask = 0xff,
24 .def = 0x0,
28 .id = 0x01,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
39 .mask = 0xff,
[all …]
H A Dtegra210.c21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
27 .mask = 0xff,
28 .def = 0x1e,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
43 .mask = 0xff,
44 .def = 0x1e,
[all …]
H A Dtegra114.c15 .id = 0x00,
20 .reg = 0x34c,
21 .shift = 0,
22 .mask = 0xff,
23 .def = 0x0,
27 .id = 0x01,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
38 .mask = 0xff,
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_ppe_regs.h7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
[all …]
/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp43x.dtsi13 /* Uses at least up to 0x230 */
14 reg = <0xc4000000 0x1000>;
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-apmixedsys.c15 #define REG_REF2USB 0x8
16 #define REG_AP_PLL_CON7 0x1c
17 #define MD1_MTCMOS_OFF BIT(0)
23 #define MT6795_CON0_EN BIT(0)
43 .pll_en_bit = 0, \
47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
48 21, 0x204, 24, 0x0, 0x204, 0),
49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
50 21, 0x220, 4, 0x0, 0x224, 0),
51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
[all …]
H A Dclk-mt8173-apmixedsys.c17 #define REGOFF_REF2USB 0x8
18 #define REGOFF_HDMI_REF 0x40
52 { .div = 0, .freq = MT8173_PLL_FMAX },
61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
62 21, 0x204, 24, 0x0, 0x204, 0),
63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
64 21, 0x214, 24, 0x0, 0x214, 0),
65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
66 0x220, 4, 0x0, 0x224, 0),
67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
[all …]
/linux/arch/powerpc/include/asm/
H A Dtsi108_pci.h12 #define TSI108_PCI_P2O_BAR0 (TSI108_PCI_OFFSET + 0x10)
13 #define TSI108_PCI_P2O_BAR0_UPPER (TSI108_PCI_OFFSET + 0x14)
14 #define TSI108_PCI_P2O_BAR2 (TSI108_PCI_OFFSET + 0x18)
15 #define TSI108_PCI_P2O_BAR2_UPPER (TSI108_PCI_OFFSET + 0x1c)
16 #define TSI108_PCI_P2O_PAGE_SIZES (TSI108_PCI_OFFSET + 0x4c)
17 #define TSI108_PCI_PFAB_BAR0 (TSI108_PCI_OFFSET + 0x204)
18 #define TSI108_PCI_PFAB_BAR0_UPPER (TSI108_PCI_OFFSET + 0x208)
19 #define TSI108_PCI_PFAB_IO (TSI108_PCI_OFFSET + 0x20c)
20 #define TSI108_PCI_PFAB_IO_UPPER (TSI108_PCI_OFFSET + 0x210)
21 #define TSI108_PCI_PFAB_MEM32 (TSI108_PCI_OFFSET + 0x214)
[all …]
/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dhci_quirks.c15 #define HCI_SCL_I3C_OD_TIMING 0x214
16 #define HCI_SCL_I3C_PP_TIMING 0x218
17 #define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230
20 #define AMD_SCL_I3C_OD_TIMING 0x00cf00cf
21 #define AMD_SCL_I3C_PP_TIMING 0x00160016
23 #define QUEUE_THLD_CTRL 0xD0
/linux/sound/isa/gus/
H A Dgusclassic.c27 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
30 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x230,0x240,0x250,0x260 */
34 static int joystick_dac[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 29};
35 /* 0 to 31, (0.59V-4.52V or 0.389V-2.98V) */
36 static int channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 24};
37 static int pcm_channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
69 static const long possible_ports[] = {0x220, 0x230, 0x240, 0x250, 0x260}; in snd_gusclassic_create()
77 if (irq[n] < 0) { in snd_gusclassic_create()
84 if (dma1[n] < 0) { in snd_gusclassic_create()
91 if (dma2[n] < 0) { in snd_gusclassic_create()
[all …]
H A Dgusmax.c25 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
28 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x230,0x240,0x250,0x260 */
32 static int joystick_dac[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 29};
33 /* 0 to 31, (0.59V-4.52V or 0.389V-2.98V) */
34 static int channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 24};
35 static int pcm_channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
71 snd_gf1_i_write8(gus, SNDRV_GF1_GB_RESET, 0); /* reset GF1 */ in snd_gusmax_detect()
73 if ((d & 0x07) != 0) { in snd_gusmax_detect()
74 dev_dbg(gus->card->dev, "[0x%lx] check 1 failed - 0x%x\n", gus->gf1.port, d); in snd_gusmax_detect()
81 if ((d & 0x07) != 1) { in snd_gusmax_detect()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/linux/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c80 DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
121 DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
167 * 0 0 0 15 x200/3 x208/2 x106
168 * 0 0 1 15 x200/3 x208/2 x88
169 * 0 1 0 20 x150/3 x156/2 x80
170 * 0 1 1 20 x150/3 x156/2 x66
171 * 1 0 0 26 / 2 x230/3 x240/2 x122
172 * 1 0 1 26 / 2 x230/3 x240/2 x102
173 * 1 1 0 30 / 2 x200/3 x208/2 x106
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/linux/Documentation/devicetree/bindings/arm/omap/
H A Dctrl.txt41 reg = <0x2000 0x2000>;
44 ranges = <0 0x2000 0x2000>;
49 reg = <0x30 0x230>;
51 #size-cells = <0>;
55 pinctrl-single,function-mask = <0xff1f>;
60 reg = <0x270 0x330>;
66 #size-cells = <0>;
76 #clock-cells = <0>;
80 reg = <0x02d8>;
/linux/Documentation/mm/
H A Dpage_owner.rst81 post_alloc_hook+0x177/0x1a0
82 get_page_from_freelist+0xd01/0xd80
83 __alloc_pages+0x39e/0x7e0
84 allocate_slab+0xbc/0x3f0
85 ___slab_alloc+0x528/0x8a0
86 kmem_cache_alloc+0x224/0x3b0
87 sk_prot_alloc+0x58/0x1a0
88 sk_alloc+0x32/0x4f0
89 inet_create+0x427/0xb50
90 __sock_create+0x2e4/0x650
[all …]
/linux/drivers/hid/
H A Dhid-ezkey.c30 return 0; in ez_input_mapping()
33 case 0x230: ez_map_key(BTN_MOUSE); break; in ez_input_mapping()
34 case 0x231: ez_map_rel(REL_WHEEL); break; in ez_input_mapping()
40 case 0x232: ez_map_rel(REL_HWHEEL); break; in ez_input_mapping()
42 return 0; in ez_input_mapping()
52 return 0; in ez_event()
61 return 0; in ez_event()
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
/linux/include/linux/
H A Dsm501-regs.h11 #define SM501_SYS_CONFIG (0x000000)
14 #define SM501_SYSTEM_CONTROL (0x000000)
16 #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
21 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
35 #define SM501_MISC_CONTROL (0x000004)
37 #define SM501_MISC_BUS_SH (0x0)
38 #define SM501_MISC_BUS_PCI (0x1)
39 #define SM501_MISC_BUS_XSCALE (0x2)
40 #define SM501_MISC_BUS_NEC (0x6)
41 #define SM501_MISC_BUS_MASK (0x7)
[all …]
/linux/sound/soc/fsl/
H A Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]

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