/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx51-zii-rdu1.dts | 21 reg = <0x90000000 0>; 31 #clock-cells = <0>; 38 pinctrl-0 = <&pinctrl_clk26mhz>; 40 #clock-cells = <0>; 47 pinctrl-0 = <&pinctrl_usbgate26mhz>; 49 #clock-cells = <0>; 56 pinctrl-0 = <&pinctrl_sndgate26mhz>; 58 #clock-cells = <0>; 81 pinctrl-0 [all...] |
H A D | imx51-zii-scu3-esb.dts | 22 reg = <0x90000000 0>; 32 pinctrl-0 = <&pinctrl_usb_mmc_reset>; 44 pinctrl-0 = <&pinctrl_ecspi1>; 49 pmic@0 { 52 pinctrl-0 = <&pinctrl_pmic>; 55 reg = <0>; 153 #size-cells = <0>; 154 led-control = <0x0 0x0 0x3f83f8 0x0>; 181 pinctrl-0 = <&pinctrl_esdhc1>; 192 pinctrl-0 = <&pinctrl_esdhc4>; [all …]
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H A D | imx51-zii-scu2-mezz.dts | 22 reg = <0x90000000 0>; 32 pinctrl-0 = <&pinctrl_usb_mmc_reset>; 43 pinctrl-0 = <&pinctrl_swmdio>; 47 #size-cells = <0>; 49 switch@0 { 51 reg = <0>; 52 dsa,member = <0 0>; 61 #size-cells = <0>; 63 port@0 { 64 reg = <0>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | omap3-overo-alto35-common.dtsi | 19 pinctrl-0 = <&led_pins>; 41 #size-cells = <0>; 43 pinctrl-0 = <&button_pins>; 56 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ 57 OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ 58 OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */ 59 OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 67 OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */
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H A D | omap3-n950-n9.dtsi | 12 cpu@0 { 19 reg = <0x80000000 0x40000000>; /* 1 GB */ 47 pinctrl-0 = <&debug_leds>; 54 #clock-cells = <0>; 62 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ 63 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ 69 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ 75 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ 76 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ 77 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ [all …]
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H A D | omap3-zoom3.dts | 15 cpu@0 { 22 reg = <0x80000000 0x20000000>; /* 512 MB */ 39 pinctrl-0 = <&wl12xx_gpio>; 54 OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 55 OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 56 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 57 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 58 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 59 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 65 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ [all …]
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H A D | omap3-evm-processor-common.dtsi | 8 reg = <0x80000000 0x10000000>; /* 256 MB */ 13 pinctrl-0 = <&wl12xx_gpio>; 21 pinctrl-0 = < 29 pinctrl-0 = <&ehci_phy_pins>; 34 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; 38 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 39 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 40 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 41 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 43 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ [all …]
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H A D | omap3-lilly-a83x.dtsi | 13 bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; 18 reg = <0x80000000 0x8000000>; /* 128 MB */ 50 #phy-cells = <0>; 59 OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ 65 OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ 71 OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ 81 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ 82 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ 83 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ 84 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ [all …]
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H A D | omap3-n900.dts | 46 cpu@0 { 58 pinctrl-0 = <&debug_leds>; 64 reg = <0x80000000 0x10000000>; /* 256 MB */ 117 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ 156 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; 164 ti,clock-source = <0x00>; /* timer_sys_ck */ 169 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ 181 #clock-cells = <0>; 190 pinctrl-0 = <&camera_pins>; 200 data-lanes = <0>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/ |
H A D | stingray-pcie.dtsi | 8 reg = <0 0x60400000 0 0x1000>; 11 bus-range = <0x0 0x1>; 16 ranges = <0x83000000 0 0x10000000 0 [all...] |
/freebsd/sys/contrib/device-tree/Bindings/media/ |
H A D | qcom,sc7280-venus.yaml | 103 reg = <0x0aa00000 0xd0600>; 119 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 120 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 123 iommus = <&apps_smmu 0x2180 0x20>, 124 <&apps_smmu 0x2184 0x20>; 137 iommus = <&apps_smmu 0x21a2 0x0>;
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | sc7280-chrome-common.dtsi | 32 CLUSTER_SLEEP_0: cluster-sleep-0 { 34 arm,psci-suspend-param = <0x40003444>; 44 reg = <0x0 0x8ad00000 0x0 0x500000>; 49 reg = <0x0 0x8b200000 0x0 0x500000>; 94 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; 97 spi_flash: flash@0 { 99 reg = <0>; 127 qcom,halt-regs = <&tcsr_1 0x17000>; 129 firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; 140 iommus = <&apps_smmu 0x2180 0x20>, [all …]
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H A D | sc7280.dtsi | 81 #clock-cells = <0>; 87 #clock-cells = <0>; 98 reg = <0x0 0x004cd000 0x0 0x1000>; 102 reg = <0x0 0x80000000 0x0 0x600000>; 107 reg = <0x0 0x80600000 0x0 0x200000>; 112 reg = <0x0 0x80800000 0x0 0x60000>; 117 reg = <0x0 0x80860000 0x0 0x20000>; 123 reg = <0x0 0x80884000 0x0 0x10000>; 128 reg = <0x0 0x808ff000 0x0 0x1000>; 133 reg = <0x0 0x80900000 0x0 0x200000>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/ |
H A D | imx23-pinfunc.h | 13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 [all …]
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H A D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 [all …]
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/freebsd/sys/contrib/alpine-hal/ |
H A D | al_hal_udma_regs_gen.h | 58 /* [0x0] Reserved register for the interrupt controller */ 60 /* [0x4] Revision register */ 62 /* [0x8] Reserved for future use */ 64 /* [0xc] Reserved for future use */ 66 /* [0x10] Reserved for future use */ 68 /* [0x14] Reserved for future use */ 70 /* [0x18] General timer configuration */ 76 * [0x0] Mailbox interrupt generator. 80 /* [0x4] Mailbox message data out */ 82 /* [0x8] Mailbox message data in */ [all …]
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/freebsd/sys/dev/bge/ |
H A D | if_bgereg.h | 54 * device register space at offset 0x8000 to read any 32K chunk 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 64 #define BGE_PAGE_ZERO 0x00000000 65 #define BGE_PAGE_ZERO_END 0x000000FF 66 #define BGE_SEND_RING_RCB 0x00000100 67 #define BGE_SEND_RING_RCB_END 0x000001FF 68 #define BGE_RX_RETURN_RING_RCB 0x00000200 69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70 #define BGE_STATS_BLOCK 0x00000300 71 #define BGE_STATS_BLOCK_END 0x00000AFF [all …]
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/freebsd/sys/dev/arcmsr/ |
H A D | arcmsr.h | 64 #define FALSE 0 67 # define INTR_ENTROPY 0 71 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 87 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 88 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 91 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 92 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 93 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ [all …]
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/freebsd/tools/test/iconv/ref/ |
H A D | UTF-16BE-rev | 1 0x00 = 0x0000 2 0x01 = 0x0100 3 0x02 = 0x0200 4 0x03 = 0x0300 5 0x04 = 0x0400 6 0x05 = 0x0500 7 0x06 = 0x0600 8 0x07 = 0x0700 9 0x08 = 0x0800 10 0x09 = 0x0900 [all …]
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H A D | UTF-16LE-rev | 1 0x00 = 0x0000 2 0x01 = 0x0001 3 0x02 = 0x0002 4 0x03 = 0x0003 5 0x04 = 0x0004 6 0x05 = 0x0005 7 0x06 = 0x0006 8 0x07 = 0x0007 9 0x08 = 0x0008 10 0x09 = 0x0009 [all …]
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H A D | BIG5HKSCS-rev | 1 0x00 = 0x00 2 0x01 = 0x01 3 0x02 = 0x02 4 0x03 = 0x03 5 0x04 = 0x04 6 0x05 = 0x05 7 0x06 = 0x06 8 0x07 = 0x07 9 0x08 = 0x08 10 0x09 = 0x09 [all …]
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/freebsd/share/i18n/csmapper/GB/ |
H A D | GB18030%UCS@BMP.src | 30 SRC_ZONE 0x81-0x84 / 0x30-0x39 / 0x81-0xFE / 0x30-0x39 / 8 32 DST_ILSEQ 0xFFFE 71 # for (i = 0; i < ncharset; ++i) { 74 # charsets[i], charsets[i + off], 0, &norm); 75 # if (ret != 0) 86 # for (i = 0; i < ncharset; ++i) 96 # for (i = 0; i < ncharset; i += 2) { 98 # if (ret == 0) { 101 # if (ret == 0 && tmp == src) 105 # return 0; [all …]
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H A D | UCS@BMP%GB18030.src | 30 SRC_ZONE 0x0080-0xFFFD 32 DST_INVALID 0xFFFFFFFF 36 0x0080 = 0x81308130 37 0x0081 = 0x81308131 38 0x0082 = 0x81308132 39 0x0083 = 0x81308133 40 0x0084 = 0x81308134 41 0x0085 = 0x81308135 42 0x0086 = 0x81308136 43 0x0087 = 0x81308137 [all …]
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/freebsd/tools/tools/locale/etc/charmaps/ |
H A D | GB18030.TXT | 5 0x03 0x0003 6 0x04 0x0004 7 0x05 0x0005 8 0x06 0x0006 9 0x07 0x0007 10 0x08 0x0008 11 0x09 0x0009 12 0x0A 0x000A 13 0x0B 0x000B 14 0x0C 0x000C [all …]
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/freebsd/share/i18n/csmapper/ISO-8859/ |
H A D | UCS%ISO-8859-2.src | 5 SRC_ZONE 0x0000-0xFFFF 7 DST_INVALID 0x100 44 # Column #1 is the ISO/IEC 8859-2 code (in hex as 0xXX) 45 # Column #2 is the Unicode (in hex as 0xXXXX) 61 0x0000-0x007F = 0x00- 62 0x0080 = 0x80 63 0x0081 = 0x81 64 0x0082 = 0x82 65 0x0083 = 0x83 66 0x0084 = 0x84 [all …]
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