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/linux/Documentation/devicetree/bindings/media/
H A Drenesas,ceu.yaml69 reg = <0xe8210000 0x209c>;
79 vsync-active = <0>;
/linux/Documentation/devicetree/bindings/soc/spacemit/
H A Dspacemit,k1-syscon.yaml89 reg = <0xd4050000 0x209c>;
/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/linux/sound/soc/codecs/
H A Dmax98396.h11 #define MAX98396_R2000_SW_RESET 0x2000
12 #define MAX98396_R2001_INT_RAW1 0x2001
13 #define MAX98396_R2002_INT_RAW2 0x2002
14 #define MAX98396_R2003_INT_RAW3 0x2003
15 #define MAX98396_R2004_INT_RAW4 0x2004
16 #define MAX98396_R2006_INT_STATE1 0x2006
17 #define MAX98396_R2007_INT_STATE2 0x2007
18 #define MAX98396_R2008_INT_STATE3 0x2008
19 #define MAX98396_R2009_INT_STATE4 0x2009
20 #define MAX98396_R200B_INT_FLAG1 0x200B
[all …]
/linux/drivers/clk/samsung/
H A Dclk-fsd.c23 /* Register Offset definitions for CMU_CMU (0x11c10000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0
25 #define PLL_LOCKTIME_PLL_SHARED1 0x4
26 #define PLL_LOCKTIME_PLL_SHARED2 0x8
27 #define PLL_LOCKTIME_PLL_SHARED3 0xc
28 #define PLL_CON0_PLL_SHARED0 0x100
29 #define PLL_CON0_PLL_SHARED1 0x120
30 #define PLL_CON0_PLL_SHARED2 0x140
31 #define PLL_CON0_PLL_SHARED3 0x160
32 #define MUX_CMU_CIS0_CLKMUX 0x1000
[all …]
H A Dclk-exynos990.c28 /* Register Offset definitions for CMU_TOP (0x1a330000) */
29 #define PLL_LOCKTIME_PLL_G3D 0x0000
30 #define PLL_LOCKTIME_PLL_MMC 0x0004
31 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
32 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
33 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
34 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
35 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
36 #define PLL_CON0_PLL_G3D 0x0100
37 #define PLL_CON3_PLL_G3D 0x010c
[all …]
/linux/drivers/media/platform/samsung/s5p-mfc/
H A Dregs-mfc.h20 #define S5P_FIMV_START_ADDR 0x0000
21 #define S5P_FIMV_END_ADDR 0xe008
23 #define S5P_FIMV_SW_RESET 0x0000
24 #define S5P_FIMV_RISC_HOST_INT 0x0008
27 #define S5P_FIMV_HOST2RISC_CMD 0x0030
28 #define S5P_FIMV_HOST2RISC_ARG1 0x0034
29 #define S5P_FIMV_HOST2RISC_ARG2 0x0038
30 #define S5P_FIMV_HOST2RISC_ARG3 0x003c
31 #define S5P_FIMV_HOST2RISC_ARG4 0x0040
34 #define S5P_FIMV_RISC2HOST_CMD 0x0044
[all …]
/linux/include/linux/mfd/mt6357/
H A Dregisters.h10 #define MT6357_TOP0_ID 0x0
11 #define MT6357_TOP0_REV0 0x2
12 #define MT6357_TOP0_DSN_DBI 0x4
13 #define MT6357_TOP0_DSN_DXI 0x6
14 #define MT6357_HWCID 0x8
15 #define MT6357_SWCID 0xa
16 #define MT6357_PONSTS 0xc
17 #define MT6357_POFFSTS 0xe
18 #define MT6357_PSTSCTL 0x10
19 #define MT6357_PG_DEB_STS0 0x12
[all …]
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/linux/fs/exfat/
H A Dnls.c16 #define UTBL_COUNT (0x10000)
24 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
25 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
26 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
27 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
28 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
29 0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
30 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
31 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
32 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json3 "EventCode": "0x3084",
8 "EventCode": "0xF880",
13 "EventCode": "0x4088",
18 "EventCode": "0x20A4",
23 "EventCode": "0x40008",
28 "EventCode": "0x20064",
33 "EventCode": "0x260B4",
38 "EventCode": "0x20006",
43 "EventCode": "0x201E4",
48 "EventCode": "0x4E044",
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dother.json3 "EventCode": "0x1f05e",
9 "EventCode": "0x2006e",
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
15 "EventCode": "0x4e05e",
17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel…
21 "EventCode": "0x610050",
27 "EventCode": "0x520050",
33 "EventCode": "0x620052",
39 "EventCode": "0x610052",
45 "EventCode": "0x610054",
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da4xx.xml10 <value name="RB4_A8_UNORM" value="0x01"/>
11 <value name="RB4_R8_UNORM" value="0x02"/>
12 <value name="RB4_R8_SNORM" value="0x03"/>
13 <value name="RB4_R8_UINT" value="0x04"/>
14 <value name="RB4_R8_SINT" value="0x05"/>
16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19 <value name="RB4_R8G8_UNORM" value="0x0f"/>
20 <value name="RB4_R8G8_SNORM" value="0x10"/>
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
H A Ddcn_3_0_3_offset.h12 // base address: 0x0
13 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
14 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
15 …VGA_MEM_READ_PAGE_ADDR 0x0001
16 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
17 …VGA_RENDER_CONTROL 0x0000
19 …VGA_SEQUENCER_RESET_CONTROL 0x0001
21 …VGA_MODE_CONTROL 0x0002
23 …VGA_SURFACE_PITCH_SELECT 0x0003
25 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_2_0_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_3_2_1_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
/linux/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_10_3_0_offset.h25 …SQ_DEBUG_STS_GLOBAL 0x10A9
26 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
27 …SQ_DEBUG_STS_GLOBAL2 0x10B0
28 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
29 …SQ_DEBUG 0x10B1
30 …ne mmSQ_DEBUG_BASE_IDX 0
33 // base address: 0x4980
34 …SDMA0_DEC_START 0x0000
35 …ne mmSDMA0_DEC_START_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
[all …]

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