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/linux/arch/arm/boot/dts/marvell/
H A Dorion5x.dtsi24 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
25 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
28 clocks = <&core_clk 0>;
34 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
35 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
38 clocks = <&core_clk 0>;
44 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
45 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
48 clocks = <&core_clk 0>;
54 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
H A Darmada-370-xp.dtsi29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
[all …]
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
H A Ddove.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
[all …]
H A Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dmarvell,orion-timer.yaml40 reg = <0x20300 0x20>;
42 clocks = <&core_clk 0>;
H A Dmarvell,armada-370-timer.yaml33 - description: Global timer interrupt 0
84 reg = <0x20300 0x30>, <0x21040 0x30>;
/linux/Documentation/devicetree/bindings/watchdog/
H A Dmarvel.txt41 reg = <0x20300 0x28>, <0x20108 0x4>;
/linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/
H A Dhclgevf_main.h20 #define HCLGEVF_MISC_VECTOR_NUM 0
22 #define HCLGEVF_INVALID_VPORT 0xffff
32 #define HCLGEVF_VECTOR_REG_BASE 0x20000
33 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
34 #define HCLGEVF_VECTOR_REG_OFFSET 0x4
35 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000
38 #define HCLGEVF_GRO_EN_REG 0x28000
39 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008
42 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
43 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi23 #size-cells = <0>;
87 reg = <0x20000>;
95 reg = <0x20001>;
103 reg = <0x20002>;
111 reg = <0x20003>;
119 reg = <0x20100>;
127 reg = <0x20101>;
135 reg = <0x20102>;
143 reg = <0x20103>;
151 reg = <0x20200>;
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt7001-pmgr.dtsi11 reg = <0x20000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x20008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x20010 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x20040 4>;
[all …]
H A Dt7000-pmgr.dtsi10 reg = <0x20000 4>;
11 #power-domain-cells = <0>;
12 #reset-cells = <0>;
19 reg = <0x20008 4>;
20 #power-domain-cells = <0>;
21 #reset-cells = <0>;
28 reg = <0x20040 4>;
29 #power-domain-cells = <0>;
30 #reset-cells = <0>;
37 reg = <0x201f8 4>;
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h31 #define HCLGE_INVALID_VPORT 0xffff
37 #define HCLGE_VECTOR_REG_BASE 0x20000
38 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000
39 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
41 #define HCLGE_VECTOR_REG_OFFSET 0x4
42 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000
43 #define HCLGE_VECTOR_VF_OFFSET 0x100000
45 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
48 #define HCLGE_GRO_EN_REG 0x28000
49 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008
[all …]
/linux/drivers/net/dsa/qca/
H A Dar9331.c54 #define AR9331_SW_REG_PAGE 0x40000
57 #define AR9331_SW_REG_GINT 0x10
58 #define AR9331_SW_REG_GINT_MASK 0x14
61 #define AR9331_SW_REG_FLOOD_MASK 0x2c
64 #define AR9331_SW_REG_GLOBAL_CTRL 0x30
65 #define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)
67 #define AR9331_SW_REG_MDIO_CTRL 0x98
73 #define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)
75 #define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100)
91 #define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv515.c47 0,
59 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
65 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
67 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
69 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
70 radeon_ring_write(ring, 0); in rv515_ring_start()
71 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
72 radeon_ring_write(ring, 0); in rv515_ring_start()
73 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
75 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi31 bus@0 {
36 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
40 reg = <0x0 0x00100000 0x0 0xf000>,
41 <0x0 0x0010f000 0x0 0x1000>;
47 reg = <0x0 0x02080000 0x0 0x00121000>;
48 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
70 reg = <0x0 0x02200000 0x0 0x10000>,
71 <0x0 0x02210000 0x0 0x10000>;
124 gpio-ranges = <&pinmux 0 0 164>;
129 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
[all …]