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Searched +full:0 +full:x20100000 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/mfd/
H A Drsmu.h13 #define RSMU_CM_SCSR_BASE 0x20100000
/linux/Documentation/devicetree/bindings/dma/
H A Dsprd,sc9860-dma.yaml74 reg = <0x20100000 0x4000>;
85 reg = <0x41580000 0x4000>;
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-stm.yaml90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi18 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
60 reg = <0x0 0x100>;
68 reg = <0x0 0x200>;
76 reg = <0x0 0x300>;
84 reg = <0x0 0x400>;
92 reg = <0x0 0x500>;
100 reg = <0x0 0x600>;
108 reg = <0x0 0x700>;
[all …]
H A Dwhale2.dtsi23 reg = <0 0x20210000 0 0x10000>;
28 reg = <0 0x402b0000 0 0x10000>;
33 reg = <0 0x402e0000 0 0x10000>;
38 reg = <0 0x40400000 0 0x10000>;
43 reg = <0 0x415e0000 0 0x1000000>;
48 reg = <0 0x61100000 0 0x10000>;
53 reg = <0 0x62100000 0 0x10000>;
58 reg = <0 0x63100000 0 0x10000>;
63 reg = <0 0x70b00000 0 0x40000>;
70 ranges = <0 0x0 0x70000000 0x10000000>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi15 #size-cells = <0>;
18 cpu0: cpu@0 {
24 reg = <0>;
189 #clock-cells = <0>;
194 mboxes = <&mbox 0>;
199 #clock-cells = <0>;
211 reg = <0x0 0x2010000 0x0 0x1000>;
223 reg = <0x0 0x2000000 0x0 0xC000>;
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
233 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
15 ranges = <0 0x0 0x2a820000 0x20000>;
20 reg = <0x10000 0x10000>;
26 reg = <0x0 0x2b1f0000 0x0 0x1000>;
37 reg = <0x0 0x2b400000 0x0 0x10000>;
49 reg = <0x0 0x2b500000 0x0 0x10000>;
60 reg = <0x0 0x2b600000 0x0 0x10000>;
66 power-domains = <&scpi_devpd 0>;
71 reg = <0x0 0x2c010000 0 0x1000>,
72 <0x0 0x2c02f000 0 0x2000>,
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/linux/lib/crypto/
H A Ddes.c30 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
31 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
32 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
33 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
34 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
35 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
36 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
37 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
38 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
39 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]