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Searched +full:0 +full:x20040000 (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/nvmem/
H A Dnxp,lpc1857-eeprom.yaml54 reg = <0x4000e000 0x1000>,
55 <0x20040000 0x4000>;
/linux/drivers/clk/rockchip/
H A Drst-rv1126b.c12 /* 0x20000000 + 0x0A00 */
13 #define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit)
14 /* 0x20010000 + 0x0A00 */
15 #define BUSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit)
16 /* 0x20020000 + 0x0A00 */
17 #define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + reg * 16 + bit)
18 /* 0x20030000 + 0x0A00 */
19 #define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000 * 4 + reg * 16 + bit)
20 /* 0x20040000 + 0x0A00 */
21 #define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x40000 * 4 + reg * 16 + bit)
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
15 ranges = <0 0x0 0x2a820000 0x20000>;
20 reg = <0x10000 0x10000>;
26 reg = <0x0 0x2b1f0000 0x0 0x1000>;
37 reg = <0x0 0x2b400000 0x0 0x10000>;
49 reg = <0x0 0x2b500000 0x0 0x10000>;
60 reg = <0x0 0x2b600000 0x0 0x10000>;
66 power-domains = <&scpi_devpd 0>;
71 reg = <0x0 0x2c010000 0 0x1000>,
72 <0x0 0x2c02f000 0 0x2000>,
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drv1108.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
42 cpu_opp_table: opp-table-0 {
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
97 reg = <0x10210000 0x100>;
106 pinctrl-0 = <&uart2m0_xfer>;
112 reg = <0x10220000 0x100>;
121 pinctrl-0 = <&uart1_xfer>;
[all …]